DAVID L THOMPSON
Nursing in Irving, TX
License number
Pennsylvania PN107529L
Category
Nursing
Type
Practical Nurse
Address
Address
2
Irving, TX 75063
Pennsylvania
Pennsylvania
Personal information
See more information about DAVID L THOMPSON at radaris.comName
Address
Phone
501 E Pioneer Pkwy APT 605, Grand Prairie, TX 75051
5006 Frank Borman Dr, San Antonio, TX 78219
501 Mason St APT 3, Phoenixville, PA 19460
503 Brown Trl APT 217, Hurst, TX 76053
502 Santone Dr, Greensburg, PA 15601
Professional information
See more information about DAVID L THOMPSON at trustoria.com
David Thompson - Irving, TX
David Thompson - Irving, TX
Work:
Seconds and Surplus - Dallas, TX
Warehouse Mobile Mini Inc - Dallas, TX
Forklift Operator Resource Personel - Addison, TX
Temp Service Lone star Container - Irving, TX
Forklift Lecor Inc - Dallas, TX
Self-Contractor CVS Pharmacy - Coppell, TX
Photo Lab Manager Ramada Inn Bay front Hotel - Corpus Christi, TX
Maintenance/Groundskeeper
Warehouse Mobile Mini Inc - Dallas, TX
Forklift Operator Resource Personel - Addison, TX
Temp Service Lone star Container - Irving, TX
Forklift Lecor Inc - Dallas, TX
Self-Contractor CVS Pharmacy - Coppell, TX
Photo Lab Manager Ramada Inn Bay front Hotel - Corpus Christi, TX
Maintenance/Groundskeeper
Skills:
Truck Driver. Forklift Operator.
Level One Data Cache Line Lock And Enhanced Snoop Protocol During Cache Victims And Writebacks To Maintain Level One Data Cache And Level Two Cache Coherence
Level One Data Cache Line Lock And Enhanced Snoop Protocol During Cache Victims And Writebacks To Maintain Level One Data Cache And Level Two Cache Coherence
US Patent:
2012019, Aug 2, 2012
Filed:
Sep 28, 2011
Appl. No.:
13/247209
Inventors:
Raguram Damodaran - Plano TX, US
Abhijeet Ashok Chachad - Plano TX, US
Jonathan (Son) Hung Tran - Murphy TX, US
David Matthew Thompson - Irving TX, US
Abhijeet Ashok Chachad - Plano TX, US
Jonathan (Son) Hung Tran - Murphy TX, US
David Matthew Thompson - Irving TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G06F 12/08
US Classification:
711122, 711E12024
Abstract:
This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.
Cache Pre-Allocation Of Ways For Pipelined Allocate Requests
Cache Pre-Allocation Of Ways For Pipelined Allocate Requests
US Patent:
2012019, Aug 2, 2012
Filed:
Sep 28, 2011
Appl. No.:
13/247222
Inventors:
Abhijeet Ashok Chachad - Plano TX, US
David Matthew Thompson - Irving TX, US
David Matthew Thompson - Irving TX, US
Assignee:
TEXAS INSTRUMENTS INCORPORATED - Dallas TX
International Classification:
G06F 12/08
US Classification:
711128, 711E12018
Abstract:
This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request according to said least recently used indication of said ways and then update the least recently used indication of remaining ways of the set. This permits read allocate requests to the same set to proceed without introducing processing stalls due to way contention. This also allows multiple outstanding allocate requests to the same set and way combination. The cache also compares the address of a newly received allocation request to stall this allocation request if the address matches an address of any pending allocation request.
Non-Blocking, Pipelined Write Allocates With Allocate Data Merging In A Multi-Level Cache System
Non-Blocking, Pipelined Write Allocates With Allocate Data Merging In A Multi-Level Cache System
US Patent:
2012019, Aug 2, 2012
Filed:
Sep 26, 2011
Appl. No.:
13/245178
Inventors:
Abhijeet Ashok Chachad - Plano TX, US
Raguram Damodaran - Plano TX, US
David Matthew Thompson - Irving TX, US
Raguram Damodaran - Plano TX, US
David Matthew Thompson - Irving TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 12/08
US Classification:
711122, 711E12024
Abstract:
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache line, merges the write data with data returned from the external memory and stores merged data in the cache. The cache controller includes buffers with plural entries storing the write address, the write data, the position of the write data within a cache line and unique identification number. This stored data enables the cache controller to proceed to servicing other access requests while waiting for response from the external memory.