DAVID JOSEPH THOMAS
Pilots at Marion Cir, Missouri City, TX
License number
Texas A5192078
Issued Date
Jun 2014
Expiration Date
Jun 2019
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3422 Marion Cir, Missouri City, TX 77459
Professional information
Method For Power Routing And Distribution In An Integrated Circuit With Multiple Interconnect Layers
US Patent:
6581201, Jun 17, 2003
Filed:
Oct 2, 2001
Appl. No.:
09/969378
Inventors:
Francisco A. Cano - Missouri City TX
David A. Thomas - Missouri City TX
Clive Bittlestone - Los Gatos CA
David A. Thomas - Missouri City TX
Clive Bittlestone - Los Gatos CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1750
US Classification:
716 12, 716 13
Abstract:
An integrated circuit has a power grid formed from a first set of power buses and on a metal interconnect level M a second set of power buses and on interconnect level M and a third set of power buses and on interconnect level M The set of power buses on level M are oriented in the same direction as the set of power buses on level M and both sets of buses are located coincidentally. A high power logic cell is pre-defined with a set of M -M power vias and so that logic cell can be positioned in a horizontal row unconstrained by pre-positioned M -M power vias. Dummy cell with M -M power vias is positioned as needed so as not to exceed a maximum strapping distance D A maximum value for distance D is selected based on dynamic power requirements of nearby logic cells as determined by simulation. A method for designing and fabricating integrated circuit is described.
Method For Power Routing And Distribution In An Integrated Circuit With Multiple Interconnect Layers
US Patent:
6308307, Oct 23, 2001
Filed:
Jan 29, 1999
Appl. No.:
9/240126
Inventors:
Francisco A. Cano - Missouri City TX
David A. Thomas - Missouri City TX
Clive Bittlestone - Los Gatos CA
David A. Thomas - Missouri City TX
Clive Bittlestone - Los Gatos CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1750
US Classification:
716 8
Abstract:
An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.