David Edward Carey
Engineers at Rickerhill Ln, Austin, TX

5091339, Feb 25, 1992

Jul 23, 1990

7/557427

David H. Carey - Austin TX

Microelectronics and Computer Technology Corporation - Austin TX

H01L 21283, H01L 21306

437187

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

5284548, Feb 8, 1994

Mar 3, 1993

8/025550

David H. Carey - Austin TX
David J. Burger - St. Paul MN

Microelectronics and Computer Technology Corporation - Austin TX
Minnesota Mining and Manufacturing Company - St. Paul MN

B44C 122, C23F 100

156630

A process for producing fine pitch surface features on a multilayer printed circuit boards such as copper-polyimide interconnects without requiring a thick copper plating foil. Initially, a thin first conductor (less than 1 micron) is vacuum deposited on a dielectric base and the dielectric base is disposed on a substrate. The substrate is then laminated and through-holes are formed therethrough. A plating seed is deposited in the through-holes and resist is patterned on the first conductor. A second conductor is deposited on the exposed portions of the first conductor and on the sidewalls, the resist is stripped and the portions or the first conductor beneath the resist are removed using a brief wet chemical etch to form spaced features without significant undercut. In the preferred embodiment, vacuum deposition occurs in a continuous roll sputtering system.

5173442, Dec 22, 1992

Mar 24, 1992

7/857011

David H. Carey - Austin TX

Microelectronics and Computer Technology Corporation - Austin TX

H01L 21283, H01L 21306

437173

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

5039628, Aug 13, 1991

Feb 12, 1990

7/479487

David H. Carey - Austin TX

Microelectronics & Computer Technology Corporation - Austin TX

H01L 2316

437183

A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more density since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

5132878, Jul 21, 1992

Apr 25, 1989

7/344534

David H. Carey - Austin TX

Microelectronics and Computer Technology Corporation - Austin TX

H05K 111

361410

A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the intergrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

5101553, Apr 7, 1992

Apr 29, 1991

7/693264

David H. Carey - Austin TX
David M. Sigmond - Austin TX

Microelectronics and Computer Technology Corporation - Austin TX

H02G 1500

29882

A method of making a metal-on-elastomer pressure contact connector. The method includes embedding a plurality of parallel co-planar copper-beryllia wires comprising a plurality of coils in a silicone rubber elastomer with top and bottom surfaces, and removing metal from the tops and bottoms of the coils to form a pair of isolated wire filaments from each coil which extend from the top surface to the bottom surface of the elastomer. The filaments form arrays of electrical contacts above and below the elastomer exceeding 10,000 contacts per square inch.

5438166, Aug 1, 1995

Nov 23, 1992

7/979541

David H. Carey - Austin TX
Barry H. Whalen - Los Alto CA

Microelectronics and Computer Technology Corporation - Austin TX

H05K 102

174261

A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements.

4829242, May 9, 1989

Dec 7, 1987

7/129495

David H. Carey - Austin TX
Roger B. Jennings - New York NY

Microelectronics and Computer Technology Corporation - Austin TX

G01R 3100

324158P

A multigigahertz probe for testing electrical micro connections or wafers. A body has a top, bottom and a testing tip at one end, and the one end slants upwardly and inwardly from the bottom towards the top. At least one coaxial cable is carried by the body and includes a first connector end and a second testing end forming testing contacts. The testing end extends to the intersection of the bottom and the slanting one end of the body.

5049979, Sep 17, 1991

Jun 18, 1990

7/539632

Seyed H. Hashemi - Austin TX
David H. Carey - Austin TX

Microelectronics and Computer Technology Corporation - Austin TX

H01L 2312, H01L 2314, H01L 2352

357 75

A capacitor, having an area smaller than the top area of a chip, is attached above the top of a tape-automated-bonded (TAB) chip and short bonded wires or TAB leads interconnect the capacitor electrodes with the power and ground pads on the chip. The interconnections are made as short as possible, with a maximum distance therebetween and with the greatest number which will reduce the inductance of the leads. The power and ground pads may contain inwardly extending bonding regions for wire bonds or flip chip capacitor attachment.