David B. Anderson
Engineers at Dreyfus Ave, Scottsdale, AZ

5500624, Mar 19, 1996

Nov 2, 1994

8/333466

David J. Anderson - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H03F 345

330253

A CMOS amplifier input stage (10) has an n-channel differential input transistor pair (12, 14) and a p-channel differential input pair (26, 28) for receiving an input signal (V. sub. p, V. sub. m). Each transistor pair is respectively coupled to current shunt transistors (20, 32) and to current source transistors (16, 30) that generate currents that are inversely proportional to transistor mobilities. Bias generators (24, 34) apply a voltage to the gates of the shunting transistors respectively. When the input stage receives a common mode signal equal to the voltage applied by the bias generators, three-fourths of transistor (16) current flows through shunt transistor (20). Likewise, three-fourths of transistor (30) current flows through shunt transistor (32). As a result, the transconductance of the n-channel differential input transistor pair is matched to the transconductance of the p-channel differential input pair, and the transconductance of the input stage remains constant throughout the common mode range for the input stage of the amplifier.

5493246, Feb 20, 1996

Sep 6, 1994

8/300906

David J. Anderson - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H03K 1716

327382

A field programmable analog array cell (10) uses programmable impedance blocks (12, 18, 22, 24) in the feed-forward and feed-back paths of an amplifier (14) to set the overall function of the array. The impedance blocks use switches (34, 38, 42, 46) to program the desired impedance value. The switches induce leakage currents into the amplifier inputs which cause drift in the output voltage. A compensation circuit (28) providing a compensation current of opposite polarity to the leakage current to the same amplifier input to cancel its effects. Alternately, a compensation circuit (30) provides a compensation current having the same polarity as the leakage current to the opposite amplifier input to cancel its effects. A p-channel transistor (50) and n-channel transistor (54) are sized to one-half the total diffusion area of like semiconductor devices in the switching circuits.

5550503, Aug 27, 1996

Apr 28, 1995

8/430999

Doug Garrity - Gilbert AZ
David Anderson - Scottsdale AZ
Howard Anderson - Tempe AZ
Brad Gunter - Phoenix AZ
Danny Bersch - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H03K 17687

327437

A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

6304140, Oct 16, 2001

Jun 12, 2000

9/592216

Christopher P. Thron - Austin TX
Michael B. Thomas - Chandler AZ
David J. Anderson - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H03F 126, G01R 1900, H04K 102

330149

A method for predistorting a digital signal prior to amplification is disclosed in which a look-up table is computed using power values of digital input signal samples as look-up values. The look-up table is preferably a function of pre-measured calibration data. The look-up table is applied to digital input signals for producing the predistorted signal. Computing the look-up table may include determining a set of input power values, obtaining the pre-measured calibration data including an output power data value and phase data value of the amplifier corresponding to each of the input power values, and deriving a set of calibration power values using the output power data values. The calibration power values and the input power values are then used to derive amplitude predistortion calibration values while the phase data values are used to determine phase predistortion calibration values. The calibration power values and corresponding amplitude predistortion calibration values are interpolated to provide amplitude predistortion values while the calibration power values and corresponding phase predistortion calibration values are interpolated to provide phase predistortion values. The look-up table is computed from the amplitude predistortion values and the phase predistortion values.

6272669, Aug 7, 2001

Dec 15, 1997

8/990694

Howard C. Anderson - Tempe AZ
Cezary Marcjan - Redmond WA
David J. Anderson - Scottsdale AZ
Danny A. Bersch - Gilbert AZ

Motorola, Inc. - Schaumburg IL

G06F 1750

716 16

A method is provided for configuring a programmable semiconductor device. The method includes using the configuration data of a macro (53A) or a plurality of macros to configure the programmable semiconductor device. The configuration data of the macro (53A) is combined with the configuration data of a work area (10). The programmable semiconductor device is configured using the combined configuration data of the macro (53A) and the work area (10).

5936469, Aug 10, 1999

Aug 4, 1997

8/905524

Daniel D. Alexander - Gilbert AZ
David J. Anderson - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H03F 345

330258

A circuit and method control the common-mode potential at an output (17, 18) of a fully differential amplifier (32) by feeding forward a common-mode correction signal through the amplifier. An input signal (V. sub. IN+ -V. sub. IN-) is amplified in the amplifier to produce a differential output signal (V. sub. O- -V. sub. O+) at the output. A common potential of the differential inputs (37, 38) of the amplifier is sensed with a transistor (54, 56) biased to a reference voltage (V. sub. CM) and amplified through the amplifier to produce a common-mode correction signal to offset a common-mode component of the differential output signal. A feedback circuit (33-36) is used to develop the common potential from the common-mode component.

5929662, Jul 27, 1999

Nov 4, 1997

8/963627

Daniel D. Alexander - Gilbert AZ
David J. Anderson - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H03K 522, H03K 302, H03K 3037

327 67

A comparator (12) and method compare first and second signals (V. sub. IN+, V. sub. IN-) to provide an output signal (V. sub. O, V. sub. OB). A transistor (43) couples a supply terminal (64, 66) of the comparator to a power supply (V. sub. DD) to enable the comparator for comparing the first and second signals. When the output signal is valid, it turns off the transistor to isolates the supply terminal from the power supply. As a result, power is reduced and a change in the first and second signals is prevented from changing the output signal. When the transistor turns off, a charge is trapped on the supply terminal that unbalances the comparator and causes a comparison error. A balanced condition is restored with a discharge circuit (31-33) coupled to the supply terminal to alter the charge when a control signal (RESET) is applied.

5691664, Nov 25, 1997

Jan 16, 1996

8/586503

David J. Anderson - Scottsdale AZ
Danny A. Bersch - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H03K 326, H01L 2500

327565

A programmable analog array (10) comprises an array of configurable cells (11), each cell (11) including analog circuitry (12) and digital circuitry (14). The cells (11) are configured for a particular functional application. The digital circuitry (14) converts an analog signal generated by the analog circuitry (12) into digital control information, which is then used to adjust the analog circuitry (12). Therefore, the analog circuitry (12) and the digital circuitry (14) form a digital feedback loop. The digital feedback loop is established either within a single cell or among neighboring cells. Thus, the digital feedback loop is established without using a global data bus.

5966047, Oct 12, 1999

Mar 27, 1997

8/826179

David J. Anderson - Scottsdale AZ
Danny A. Bersch - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H03K 326, H01L 2500

327565

A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.