DR. DAVID ARTHUR BAKER, D.D.S.
Dentist at Bee Cave Rd, Austin, TX

5940610, Aug 17, 1999

Oct 3, 1996

8/720891

David C. Baker - Austin TX
Michael D. Asal - Austin TX
Jonathan I. Siann - San Diego CA
Paul B. Wood - Austin TX
Jeffrey L. Nye - Austin TX
Stephen G. Glennon - Cedar Park TX
Matthew D. Bates - Austin TX

Brooktree Corporation - San Diego CA

G06F 1300

395559

Multimedia information (e. g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying the different media. A media stream controller processes the information and passes the processed information to the display memory. Controllers in the media stream controller individually pass multimedia information to the display memory. A PACDAC controller in the media stream controller causes media (e. g. graphics, video) in the display memory to be transferred to a PACDAC for display. The format, sequence, and rate of this transfer may be flexibly controlled by software on a frame by frame basis. Arbitration logic establishes priorities for the different controllers in the media stream controller so they may share a single bus for accessing the display memory. A single interrupt controller coordinates interrupts (e. g.

2012022, Sep 13, 2012

Sep 7, 2010

13/394930

Hector Luis Moya - Austin TX, US
David Christopher Baker - Austin TX, US
Ramon Anthony Caamaño - Gilroy CA, US

GREEN RAY TECHNOLOGIES LLC - Gilroy CA

H02K 3/28, H02K 3/38, H02K 11/00

310 71, 310198

In some aspects, the present disclosure provides an electric machine including a rotor assembly having a plurality of rotor poles, and a stator assembly having a plurality of stator modules, each stator module including multiple, independently energizeable stator segments each corresponding to a segment position within the stator module. The stator modules are electrically connected to form sets of interconnected stator segments, each stator segment set including at least one stator segment from each of multiple stator modules and corresponding to a different electrical phase of the machine, and each stator segment set includes segments from different segment positions within their respective stator assemblies.

4740927, Apr 26, 1988

Feb 13, 1985

6/701328

David C. Baker - Austin TX
John S. Muhich - Austin TX

International Business Machines Corporation - Armonk NY

G11C 1300

365238

A memory array associated with a display can be accessed in either one of two substantially orthogonal directions. The memory array is structured so that it may be accessed, such as for reading or writing, in either the horizontal or vertical direction. Pel position representations in the array are arranged so that vertically sequential pel positions in a given column are represented by data in sequential memory modules rather than by data in the same memory module. Likewise, horizontally sequential pels in a given row are represented by data in sequential modules rather than in the same module. The memory array is comprised of a plurality of separate memory modules and is structured so that both x and y directional accessing into and out of the array is accomplished on a bit addressable x,y field. This enables any bit string in the array to be addressed and to be read from or written into the array in either the x or y direction. No word or byte boundaries exist in either the x direction of access or the y direction of access.

5790110, Aug 4, 1998

Jan 15, 1997

8/783777

David C. Baker - Austin TX
Daniel P. Mulligan - Austin TX
Eric J. Schell - Austin TX

Brooktree Corporation - San Diego CA

G09G 502

345202

A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing.

2012023, Sep 20, 2012

Sep 7, 2010

13/394911

Hector Luis Moya - Austin TX, US
David Christopher Baker - Austin TX, US
Ramon Anthony Caamaño - Gilroy CA, US

GREEN RAY TECHNOLOGIES LLC - Gilroy CA

H02K 3/28

310 71

In some implementations, the present disclosure provides an electric machine including a rotor assembly, a stator assembly comprising a plurality of stator modules, each stator comprising multiple, independently energizeable stator segments, each segment having a corresponding electrical connecting point, and a plurality of bus bars connected to the electrical connecting points of the stator assembly, each bus bar corresponding to a different phase of the machine and electrically connecting segments of multiple stator modules. The stator modules and their electrical connecting points are arranged such that spacing between adjacent connecting points within each stator module differs from spacing between adjacent connecting points of different modules.

6912608, Jun 28, 2005

Apr 25, 2002

10/131941

Edward A. Wolff - Chapel Hill NC, US
David Baker - Austin TX, US
Bryan Garnett Cope - Durham NC, US
Edwin Franklin Barry - Vilas NC, US

PTS Corporation - San Jose CA

G06F013/00

710100, 710 21, 712 10, 712 11, 711140, 345506

Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.

2007008, Apr 12, 2007

Oct 11, 2005

11/247740

Antonio Torrini - Austin TX, US
Robert Koelling - Austin TX, US
Romesh Mangho Jessani - Austin TX, US
David Baker - Austin TX, US

G06F 12/00

711125000

A method of executing a program using a processor is implemented by executing a first main program segment stored in a ROM device until a first ROM instruction address, corresponding to one of a first sequence of ROM instructions, matches one of a plurality of a patch addresses stored in a patch register set. In response to this matching, a first patch program segment, stored in a RAM device, is executed.