DAVID AARON KAPLAN
Pilots at Lee Barton Dr, Austin, TX
License number
Texas A5203380
Issued Date
Aug 2014
Expiration Date
Aug 2019
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
210 Lee Barton Dr UNIT 306, Austin, TX 78704
Professional information
Senior Member Of Technical Staff At Amd
Position:
Senior Member of Technical Staff at AMD
Location:
Austin, Texas Area
Industry:
Computer Hardware
Work:
AMD
- Austin, Texas Area since Jun 2006
-
Senior Member of Technical Staff
Microsoft
Jun 2005 - Aug 2005
-
SDE Intern
Education:
University of Illinois at Urbana-Champaign 2003 - 2006
Bachelor of Science (BS), Computer Engineering
Bachelor of Science (BS), Computer Engineering
Skills:
Microcode, Security, Verilog, x86, ARM, Cryptography, Architecture, CPU design, System Architecture, X86
Processor Configured To Virtualize Guest Local Interrupt Controller
US Patent:
2011019, Aug 11, 2011
Filed:
Dec 6, 2010
Appl. No.:
12/961189
Inventors:
Benjamin C. Serebrin - Sunnyvale CA, US
Rodney W. Schmidt - Dripping Springs TX, US
David A. Kaplan - Austin TX, US
Mark D. Hummel - Franklin MA, US
Rodney W. Schmidt - Dripping Springs TX, US
David A. Kaplan - Austin TX, US
Mark D. Hummel - Franklin MA, US
International Classification:
G06F 13/24, G06F 9/455
US Classification:
710267
Abstract:
In an embodiment, a guest interrupt control unit in a hardware processor may be configured to detect that an interrupt has been recorded in a memory location corresponding to a virtual processor, wherein the interrupt is targeted at the virtual processor. In response to the virtual processor being active on the hardware processor, the guest interrupt control unit is configured to provide the interrupt to the guest that includes the virtual processor. In an embodiment, a processor is configured to execute instructions from a guest, wherein the processor is configured to detect an instruction that accesses interrupt controller state data associated with a virtual processor in the guest, and wherein the processor is configured to access a memory location that stores interrupt controller state data corresponding to the virtual processor in response to the instruction.
Method And Apparatus For Controlling A Translation Lookaside Buffer
US Patent:
8341316, Dec 25, 2012
Filed:
Nov 17, 2010
Appl. No.:
12/948677
Inventors:
David Kaplan - Austin TX, US
Christopher D. Bryant - Austin TX, US
Stephen P. Thompson - Longmont CO, US
Christopher D. Bryant - Austin TX, US
Stephen P. Thompson - Longmont CO, US
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G06F 3/00, G06F 9/26
US Classification:
710 55, 710 5, 711207, 719314
Abstract:
A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal.
Register Reduction And Liveness Analysis Techniques For Program Code
US Patent:
2010009, Apr 15, 2010
Filed:
Oct 10, 2008
Appl. No.:
12/249446
Inventors:
David A. Kaplan - Austin TX, US
International Classification:
G06F 9/45
US Classification:
717156, 717154
Abstract:
A system and method for efficient architectural register liveness analysis and register usage reduction. A compiler within a computing system maintains a master liveness vector for each instruction in a program code and a path liveness vector for each path within a predetermined control flow graph (CFG). Predetermined required paths from an earlier compiler stage are used to find force paths, which are used to reduce the number of times a control block (CB) is processed. Upon completion of the liveness analysis, the compiler finds an instruction within the program code where a chosen register previously dead is now live. The compiler identifies allocation code paths from this instruction, wherein each path terminates at an instruction wherein the chosen register is dead for the first time in the allocation code path. The compiler subsequently replaces the chosen register with a determined dead register.
Oldest Operation Translation Look-Aside Buffer
US Patent:
2014006, Mar 6, 2014
Filed:
Aug 30, 2012
Appl. No.:
13/599269
Inventors:
David Kaplan - Austin TX, US
John M. King - Austin TX, US
John M. King - Austin TX, US
International Classification:
G06F 12/10, G06F 12/00, G06F 12/08
US Classification:
711108, 711207, 711144, 711E12001, 711E12037, 711E12061
Abstract:
A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.
Microcode Rename Reclamation
US Patent:
2012000, Jan 5, 2012
Filed:
Jul 1, 2010
Appl. No.:
12/828402
Inventors:
Jeffrey P. Rupley - Round Rock TX, US
David A. Kaplan - Austin TX, US
David A. Kaplan - Austin TX, US
International Classification:
G06F 12/06, G06F 12/08
US Classification:
711166, 711203, 711E12017, 711E12083
Abstract:
A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer.
Interrupt Virtualization
US Patent:
8489789, Jul 16, 2013
Filed:
Dec 6, 2010
Appl. No.:
12/961186
Inventors:
Benjamin C. Serebrin - Sunnyvale CA, US
Rodney W. Schmidt - Dripping Springs TX, US
David A. Kaplan - Austin TX, US
Mark D. Hummel - Franklin MA, US
Rodney W. Schmidt - Dripping Springs TX, US
David A. Kaplan - Austin TX, US
Mark D. Hummel - Franklin MA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 13/24, G06F 9/46
US Classification:
710267, 710260, 718102, 718105
Abstract:
In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.
Cache Scratch-Pad And Method Therefor
US Patent:
2011013, Jun 2, 2011
Filed:
Nov 27, 2009
Appl. No.:
12/626826
Inventors:
David A. Kaplan - Austin TX, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 12/08, G06F 12/14
US Classification:
711141, 711163, 711E12091, 711E12017
Abstract:
An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces.
Method And Apparatus For Handling Critical Blocking Of Store-To-Load Forwarding
US Patent:
2012005, Mar 8, 2012
Filed:
Sep 7, 2010
Appl. No.:
12/876912
Inventors:
DAVID KAPLAN - Austin TX, US
Tarun Nakra - Austin TX, US
Christopher D. Bryant - Austin TX, US
Bradley Burgess - Austin TX, US
Tarun Nakra - Austin TX, US
Christopher D. Bryant - Austin TX, US
Bradley Burgess - Austin TX, US
International Classification:
G06F 12/08, G06F 12/00
US Classification:
711 3, 711141, 711200, 711E12001, 711E12026
Abstract:
The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.
Early Branch Determination
US Patent:
2011005, Mar 3, 2011
Filed:
Aug 31, 2009
Appl. No.:
12/551240
Inventors:
David A. Kaplan - Austin TX, US
Daniel B. Hopper - Austin TX, US
Benjamin C. Serebrin - Sunnyvale CA, US
Daniel B. Hopper - Austin TX, US
Benjamin C. Serebrin - Sunnyvale CA, US
International Classification:
G06F 9/312, G06F 9/22
US Classification:
712214, 712245, 712E09005, 712E09033
Abstract:
A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. The method further includes a second command issuing, subsequent to the first command issuing, within the computer processor, wherein execution of the second command by the computer processor includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, the method includes a third command issuing within the computer processor, wherein execution of the third command by the computer processor includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.