DANIEL STASIAK, DC
Chiropractic at Broughton Way, Austin, TX

2003019, Oct 9, 2003

Apr 4, 2002

10/116245

Andrew Davies - Rochester MN, US
Daniel Stasiak - Austin TX, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F017/50

703/014000

A method and apparatus are provided for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits. A method of logical effort is applied to the CMOS logic circuits. Selected circuits within the CMOS logic circuits are checked for noise immunity utilizing a noise test simulation to identify each selected circuit failing the noise test simulation. An electrical effort is fixed to a value for providing noise immunity for each identified selected circuit failing the noise test simulation. The method of logical effort is applied to each remaining selected circuit not failing the noise test simulation. The sequential steps are repeated for each remaining selected circuit not failing the noise test simulation until no selected circuit failing the noise test simulation is identified. The selected circuits that are checked for noise immunity include, for example, dynamic circuits and passgate circuits. When none of the selected circuits fail the noise test simulation, or the electrical efforts have been fixed for all of the selected circuits failing the noise test simulation, the delay through the CMOS logic circuits has been minimized and the selected circuits are all assured of adequate noise immunity.

7725744, May 25, 2010

Jan 18, 2008

12/016706

Rajat Chaudhry - Austin TX, US
James Scott Neely - Wappingers Falls NY, US
Daniel Lawrence Stasiak - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 17/50, G06F 1/00

713300, 716 1, 716 4

A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

7343499, Mar 11, 2008

Jan 27, 2005

11/044568

Rajat Chaudhry - Austin TX, US
James Scott Neely - Wappingers Falls NY, US
Daniel Lawrence Stasiak - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 17/50, G06F 1/00

713300, 716 1, 716 4

A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

7656237, Feb 2, 2010

Dec 2, 2004

11/002559

Mack Wayne Riley - Austin TX, US
Daniel Lawrence Stasiak - Austin TX, US
Michael Fan Wang - Austin TX, US
Stephen Douglas Weitzel - Round Rock TX, US

International Business Machines Corporation - Armonk NY

H03L 7/095

331 25, 331DIG 2, 327157, 713323

An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.

7233188, Jun 19, 2007

Dec 22, 2005

11/318228

Chiaki Takano - Austin TX, US
Daniel Lawrence Stasiak - Austin TX, US
Nathan Paul Chelstrom - Cedar Park TX, US
Steven Ross Ferguson - Granite Shoals TX, US

Sony Computer Entertainment Inc. - Tokyo

G06F 1/04

327291, 713323

Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.

7605612, Oct 20, 2009

May 16, 2008

12/121827

Owen Chiang - Austin TX, US
Christopher M. Durham - Round Rock TX, US
Peter J. Klim - Austin TX, US
Daniel L. Stasiak - Austin TX, US
Albert J. Van Norstrand, Jr. - Round Rock TX, US

International Business Machines Corporation - Armonk NY

H03K 19/00

326 93, 326136, 327544, 713322

A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.

7535020, May 19, 2009

Jun 28, 2005

11/168591

Munehiro Yoshida - Austin TX, US
Daniel Stasiak - Austin TX, US
Michael F. Wang - Austin TX, US
Charles R. Johns - Austin TX, US
Hiroki Kihara - Austin TX, US
Tetsuji Tamura - Tokyo, JP
Kazuaki Yazawa - Chiba, JP
Iwao Takiguchi - Kanagawa, JP

Kabushiki Kaisha Toshiba - Tokyo
International Business Machines Corporation - Armonk NY
Sony Computer Entertainment Inc. - Tokyo

H01L 23/58

257 48, 257467, 257E29347, 257E23179

Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

7720667, May 18, 2010

Sep 8, 2006

11/530100

Rajat Chaudhry - Austin TX, US
Tilman Gloekler - Gaertringen, DE
Daniel L. Stasiak - Austin TX, US
Todd Swanson - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 17/50

703 18, 703 2, 716 1, 716 4

First hardware is for executing first software in response to macros that describe integrated circuitry, and for generating a set of constants in response to the execution of the first software. Second hardware is for receiving the set of constants from the first hardware, and for executing second software in response to the macros and the set of constants, and for estimating a power consumption of the integrated circuitry in response to the execution of the second software.

7284138, Oct 16, 2007

Dec 2, 2004

11/002551

Mack Wayne Riley - Austin TX, US
Daniel Lawrence Stasiak - Austin TX, US
Michael Fan Wang - Austin TX, US
Stephen Douglas Weitzel - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 1/00

713322, 713310, 713324

An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

8438569, May 7, 2013

Oct 14, 2004

10/965634

Michael Norman Day - Round Rock TX, US
Mark Richard Nutter - Austin TX, US
Daniel Lawrence Stasiak - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46, G06F 1/26, G06F 9/44

718101, 713320, 719318

The present invention provides for notifying threads. A determination is made whether there is a condition for which a thread is to be notified. If so, a notification indicia is broadcasted. A flag is set in at least one memory storage area as a function of the notification indicia wherein the setting the flag occurs without the intervention of an operating system. Therefore, latencies for notification of threads are minimized.