DANIEL P BAKER
Electrician at Patsy Pkwy, Austin, TX

7434124, Oct 7, 2008

Mar 28, 2006

11/391009

Daniel J. Baker - Austin TX, US
J. Christopher White - Austin TX, US
Ciro T. Nishiguchi - Austin TX, US

National Instruments Corporation - Austin TX

G01R 31/28

714724, 714 30

A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing configuration sets. Each selection code indicates an association between a test vector and a configuration set. Each configuration set may be associated with one or more of the test vectors. The configuration sets include information for configuring the interface circuits during communications between the test system and the DUT for each test vector. Each configuration set in the third memory is unique with respect to the other configuration sets, and the number of configuration sets may be less than the number of test vectors.

7478256, Jan 13, 2009

Jan 24, 2006

11/338923

Craig M. Conway - Austin TX, US
Jeff A. Bergeron - Austin TX, US
Daniel J. Baker - Austin TX, US

National Instruments Corporation - Austin TX

G06F 1/12

713401, 713501, 326 93, 327141, 327162

System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

2013022, Aug 29, 2013

Feb 22, 2013

13/774914

CIRRUS LOGIC, INC. - , US
John L. Melanson - Austin TX, US
Daniel J. Baker - Austin TX, US

CIRRUS LOGIC, INC. - Austin TX

H05B 37/02

315254

In at least one embodiment, a system and method provide current compensation in a lighting system by controlling a lamp current to prevent a current through a triac-based dimmer from undershooting a holding current value. In at least one embodiment, at least one of the lamps includes a controller that controls circuitry in the lamp to draw more lamp current for a period of time than needed to illuminate a brightness of the lamp at a level corresponding to particular phase-cut angle of the supply voltage. By drawing more current than needed, the controller increases the dimmer current during the period of time to prevent the dimmer current from falling below the holding current value. In at least one embodiment, the period of time corresponds to a compensating pulse of the lamp current at a time when the dimmer current would otherwise fall below the holding current value.

2005004, Mar 3, 2005

Aug 28, 2003

10/651124

Charles Schroeder - Round Rock TX, US
Daniel Baker - Austin TX, US
Glen Sescila - Pflugerville TX, US

H03H011/26

327276000

A delay circuit. In one embodiment, a programmable logic device (PLD) is used to implement one or more delay circuits having a plurality of delay elements. Included in the plurality of elements are a balanced number of logic elements such that rising and falling edges of a signal passing through the delay circuit propagate with substantially the same amount of delay. The delay circuit may also include a selector circuit coupled to select an output from one of the plurality of delay elements. The delay circuit may be implemented such that it preserves the duty cycle and/or pulse width of signals to which the delay is applied.