MR. DANIEL L WANG, PHARMACIST
Pharmacy at Mckee Rd, San Jose, CA

6809398, Oct 26, 2004

Dec 14, 2000

09/737642

Daniel Wang - San Jose CA

Actel Corporation - Mountain View CA

H01L 2900

257530, 257 50, 257529, 438131, 438467, 438600, 438957

A metal-to-metal antifuse according to the present invention is compatible with a Cu dual damascene process and is formed over a lower Cu metal layer planarized with the top surface of a lower insulating layer. A lower barrier layer is disposed over the lower Cu metal layer. An antifuse material layer is disposed over the lower barrier layer. An upper barrier layer is disposed over the antifuse material layer. An upper insulating layer is disposed over the upper barrier layer. An upper Cu metal layer is planarized with the top surface of the upper insulating layer and extends therethrough to make electrical contact with the upper barrier layer.

7071115, Jul 4, 2006

Feb 4, 2004

10/772932

Chunchieh Huang - Fremont CA, US
Chia-Shun Hsiao - Cupertino CA, US
Jin-Ho Kim - San Jose CA, US
Barbara Haselden - Cupertino CA, US
Daniel C. Wang - San Jose CA, US

ProMOS Technologies Inc. - Hsin Chu

H01L 21/302, H01L 21/461, H01L 21/44, H01L 21/76

438717, 438736, 438671, 438401, 438448

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

2006021, Sep 21, 2006

May 10, 2006

11/432222

Chunchieh Huang - Fremont CA, US
Chia-Shun Hsiao - Cupertino CA, US
Jin-Ho Kim - San Jose CA, US
Barbara Haselden - Cupertino CA, US
Daniel Wang - San Jose CA, US

H01L 21/302

438717000

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

2008029, Nov 27, 2008

May 23, 2007

11/752711

Daniel C. Wang - San Jose CA, US

G11C 11/34, H01L 29/788

3651853, 257315, 438257, 257E293

A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises Vand thus drives Vbelow local threshold even for over-erased transistors of the sector that have a Vde-assertion voltage applied to their control gates for purpose of turning those transistors off. In one embodiment, the variable source resistance is set to a second intermediate resistance value during a testing mode that tests the extent to which the corresponding sector has been over-erased. The results of the testing mode are then used to intelligently optimize the number of transistors that are simultaneously soft-programmed in that sector during each Vcompaction cycle.

2005009, Apr 28, 2005

Aug 27, 2004

10/929106

Frank Hawley - Campbell CA, US
Daniel Wang - San Jose CA, US

H01L021/336, H01L021/8234, H01L021/76

438197000, 438424000, 438296000

A method for fabricating a shallow-trench isolation transistor an a semi-conductor substrate includes forming a single isolation trench having a uniform cross section to define an active region in the silicon substrate. The method includes performing sidewall isolation implants on the side and bottom walls of said isolation trench. The method includes depositing a dielectric isolation material in said isolation trench. The method includes planarizing the top surface of said silicon substrate and said dielectric isolation material. The method includes forming a gate oxide layer over said active region in said silicon substrate. The method includes forming and defining gate regions over said oxide layer in said active region in said silicon substrate. The method includes forming source and drain regions in the active region in the silicon substrate.

7300745, Nov 27, 2007

Feb 4, 2004

10/772520

Chia-Shun Hsiao - Cupertino CA, US
Chunchieh Huang - Fremont CA, US
Jin-Ho Kim - San Jose CA, US
Barbara Haselden - Cupertino CA, US
Daniel C. Wang - San Jose CA, US

ProMOS Technologies Inc. - Hsin Chu

H01L 29/66, H01L 21/336

430311, 438257, 257319

Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

7358149, Apr 15, 2008

Jul 29, 2005

11/193150

Daniel Wang - San Jose CA, US
Chunchieh Huang - Fremont CA, US
Dong Jun Kim - San Jose CA, US

ProMOS Technologies, Inc. - Hsin-Chu

H01L 21/425

438433, 438525, 257E21551

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e. g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

7387942, Jun 17, 2008

Dec 9, 2003

10/732616

Daniel Wang - San Jose CA, US
Chunchieh Huang - Fremont CA, US
Dong Jun Kim - San Jose CA, US

ProMOS Technologies Inc. - Hsin-Chu

H01L 21/425, H01L 21/762

438433, 438524, 438525, 257E21345

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e. g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

2005009, Apr 28, 2005

Aug 27, 2004

10/929107

Frank Hawley - Campbell CA, US
Daniel Wang - San Jose CA, US

H01L021/8238, H01L021/8242, H01L021/336

438424000, 438296000, 438589000, 438243000, 438197000

A shallow-trench isolation includes a semiconductor substrate. Spaced apart source and drain regions define an active region in the semiconductor substrate. A single isolation trench is in the semiconductor substrate having a uniform cross-section surrounds the active region. An isolation implant is formed in the sidewalls of the isolation trench. A gate dielectric layer is formed over the active region. A gate is disposed over the gate dielectric layer and is located between the source and drain region.