DANIEL JAY MEYER
Pilots at Granite Rd, Woodstock, MD
License number
Maryland A4127919
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
2832 Granite Rd, Woodstock, MD 21163
Professional information
Daniel Meyer - Woodstock, MD
Work:
Atmel
Senior Design Engineer Orbital Sciences
Engineer Sigtek
Electrical Engineer College Park
President of Amateur Radio Association of the U of MD
Senior Design Engineer Orbital Sciences
Engineer Sigtek
Electrical Engineer College Park
President of Amateur Radio Association of the U of MD
Education:
University of Maryland - College Park, MD
MS in Electrical Engineering University of Maryland - College Park, MD
BS in Electrical Engineering University Honors Program
MS in Electrical Engineering University of Maryland - College Park, MD
BS in Electrical Engineering University Honors Program
Skills:
x86 Assembly, Verilog and Verilog-A, C, Perl, Spectre/APS/Nanosim/HSIM/FineSim/HSPICE, Diva/Assura/Calibre, Matlab/Octave, Eagle PCB, StarRC-XT/Arcadia/Fire&Ice/QX Synthesis: Design Compiler/Library Compiler Back-end: icfb, First/SOC Encounter
Discrete-Time Analog, Digitally Programmable Filter And Method
US Patent:
7769799, Aug 3, 2010
Filed:
May 13, 2005
Appl. No.:
11/128989
Inventors:
Mikhail Itskovich - Columbia MD, US
Daniel J. Meyer - Woodstock MD, US
Daniel J. Meyer - Woodstock MD, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06G 7/02
US Classification:
708819, 708300, 375350
Abstract:
Aspects provide discrete-time analog, digitally programmable filtering. A filter includes a plurality of transistors coupled as a current mode circuit. Further included is a switch for use in switching the plurality of transistors in and out to tune the current mode circuit, wherein adjustable low bandwidth filtering using small silicon area without passive components is achieved.
Voltage Regulator For An Integrated Circuit
US Patent:
8115462, Feb 14, 2012
Filed:
Jun 20, 2007
Appl. No.:
11/765805
Inventors:
Daniel Meyer - Woodstock MD, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G05F 1/59, H02M 3/18
US Classification:
323272, 323284, 327536, 363 60
Abstract:
A voltage regulator is disclosed. The voltage regulator includes a comparator for providing a gated output signal; and a state machine for receiving the gated output signal. The voltage regulator further includes at least one switch cell controlled by the state machine, for delivering charge to a load. Accordingly, a voltage regulator in accordance with the present invention yields N times (where N is an integer greater than one) the linear efficiency over typical linear regulators without requiring any external components. Therefore improved regulator efficiency is provided for low power devices.
Dual Phase Pulse Modulation Decoder Circuit
US Patent:
6947493, Sep 20, 2005
Filed:
Apr 29, 2004
Appl. No.:
10/836710
Inventors:
Daniel S. Cohen - Baltimore MD, US
Daniel J. Meyer - Woodstock MD, US
Daniel J. Meyer - Woodstock MD, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H04L027/04, H04L027/12, H04L027/20
US Classification:
375295, 341 53, 341 68
Abstract:
A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2possible data values of an M-bit group corresponds to one of 2distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and using the delayed outputs to clock flip-flop registers to sample the non-delayed signal. The registered output is interpreted by logic gates to obtain the corresponding M-bit groups. The decoder circuit may have two substantially identical pulse width determining blocks, one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.
Method For Performing Dual Phase Pulse Modulation
US Patent:
7283011, Oct 16, 2007
Filed:
Apr 29, 2004
Appl. No.:
10/836705
Inventors:
Daniel S. Cohen - Baltimore MD, US
Daniel J. Meyer - Woodstock MD, US
John L. Fagan - Pasadena MD, US
Daniel J. Meyer - Woodstock MD, US
John L. Fagan - Pasadena MD, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H03K 7/04
US Classification:
332112, 332106, 332109, 375239, 370215, 370205
Abstract:
A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2possible data values for a group of M data bits uniquely corresponds to one of 2distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.
Current Starved Dac-Controlled Delay Locked Loop
US Patent:
6927612, Aug 9, 2005
Filed:
Apr 29, 2004
Appl. No.:
10/836704
Inventors:
Daniel J. Meyer - Woodstock MD, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H03L007/06
US Classification:
327156, 327147
Abstract:
A delay locked loop circuit with improved restart features. The circuit includes a clock input, a clock output, a divider circuit, phase detector and control logic. The circuit includes a means for implementing a binary search of outputs from the control logic for generating a calibration bit, which is applied to the transmission on an output line.