DANIEL ANTHONY RODRIGUEZ, AOD COUNSELOR
Social Work at Fletcher Ln, Hayward, CA
License number
California R0412281420
Category
Social Work
Type
Addiction (Substance Use Disorder)
Address
Address
2
795 Fletcher Ln, Hayward, CA 94544
33526 4Th St, Union City, CA 94587
33526 4Th St, Union City, CA 94587
Phone
(510) 247-8300
(510) 247-8295 (Fax)
(925) 597-1575
(510) 247-8295 (Fax)
(925) 597-1575
Personal information
See more information about DANIEL ANTHONY RODRIGUEZ at radaris.comName
Address
Phone
504 Northbank Ct Apt 130, Stockton, CA 95207
504 Richards Ave, Bakersfield, CA 93307
50 Harriet Ave, San Jose, CA 95127
5042 Harvard Ave, Westminster, CA 92683
5017 Charmian Dr, Santa Rosa, CA 95409
Professional information
Memory Architecture Having Multiple Partial Wordline Drivers And Contacted And Feed-Through Bitlines
US Patent:
7697364, Apr 13, 2010
Filed:
Dec 1, 2005
Appl. No.:
11/291219
Inventors:
Raymond Jit-Hung Sung - Sunnyvale CA, US
Dongwook Suh - Saratoga CA, US
Daniel Rodriguez - Hayward CA, US
Dongwook Suh - Saratoga CA, US
Daniel Rodriguez - Hayward CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 8/00
US Classification:
36523006, 36523003, 36523002
Abstract:
Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.
Memory Architecture Having Multiple Partial Wordline Drivers And Contacted And Feed-Through Bitlines
US Patent:
8477556, Jul 2, 2013
Filed:
Jul 26, 2011
Appl. No.:
13/191107
Inventors:
Raymond J. Sung - Sunnyvale CA, US
Dongwook Suh - Saratoga CA, US
Daniel O. Rodriguez - Hayward CA, US
Dongwook Suh - Saratoga CA, US
Daniel O. Rodriguez - Hayward CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 8/00
US Classification:
36523006, 36523003, 36523002
Abstract:
Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.
Memory Architecture Having Multiple Partial Wordline Drivers And Contacted And Feed-Through Bitlines
US Patent:
8009506, Aug 30, 2011
Filed:
Mar 24, 2010
Appl. No.:
12/730873
Inventors:
Raymond J. Sung - Sunnyvale CA, US
Dongwook Suh - Saratoga CA, US
Daniel O. Rodriguez - Hayward CA, US
Dongwook Suh - Saratoga CA, US
Daniel O. Rodriguez - Hayward CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 8/00
US Classification:
36523006, 36523003, 36523002, 365203
Abstract:
Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.