Dale Morris
Electrician in Steamboat Springs, CO
License number
Colorado 951285
Issued Date
Nov 13, 1995
Renew Date
Apr 28, 2011
Type
Electrical Apprentice
Address
Address
PO Box 881473, Steamboat Springs, CO 80488
Professional information
Intra-Register Subword-Add Instructions
US Patent:
2004019, Sep 30, 2004
Filed:
Mar 31, 2003
Appl. No.:
10/403863
Inventors:
Ruby Lee - Princeton NJ, US
Dale Morris - Steamboat Springs CO, US
Dale Morris - Steamboat Springs CO, US
International Classification:
G06F009/00
US Classification:
712/221000
Abstract:
Intra-register subword add instructions yield results that are a function of a sum having as at least some of its addends unary functions of at least two subwords stored in the same register. For example, one “TreeAdd” instruction yields a sum of all subwords in a register. A “parallel accumulate” PAcc instruction yields a result with four 2-byte result subwords. Each result subword is the sum of 2-byte value in a first operand register and two of eight 1-byte subwords in a second operand register. A “Parallel Accumulate Magnitude” PAccMagLR also yields a result with four 2-byte subwords. Each of these subwords is the sum of a 2-byte value in a first operand register and the absolute values of two 1-byte values in a second operand register. These instructions provide for substantial performance enhancements for motion estimation used in video compression.
Variable Reordering (Mux) Instructions For Parallel Table Lookups From Registers
US Patent:
2004019, Sep 30, 2004
Filed:
Mar 31, 2003
Appl. No.:
10/403785
Inventors:
Ruby Lee - Princeton NJ, US
Dale Morris - Steamboat Springs CO, US
Dale Morris - Steamboat Springs CO, US
International Classification:
G06F009/44
US Classification:
712/225000, 712/022000
Abstract:
Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.
Method And System For Using Dynamic, Deferred Operation Information To Control Eager Deferral Of Control-Speculative Loads
US Patent:
6931515, Aug 16, 2005
Filed:
Jul 29, 2002
Appl. No.:
10/208095
Inventors:
Jonathan K. Ross - Woodinville WA, US
Dale Morris - Steamboat Springs CO, US
Dale Morris - Steamboat Springs CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F009/312
US Classification:
712216, 712225
Abstract:
A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk. s-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction. By contrast, if no entry corresponding to the control-speculative load instruction is found in the speculative-load-accelerated-deferral table, then the exception is immediately handled.
Multiprocessor System With Interactive Synchronization Of Local Clocks
US Patent:
7340630, Mar 4, 2008
Filed:
Aug 8, 2003
Appl. No.:
10/638696
Inventors:
Dale C. Morris - Steamboat Springs CO, US
Jonathan K. Ross - Woodinville WA, US
Jonathan K. Ross - Woodinville WA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1/04, G06F 1/12
US Classification:
713400, 713503
Abstract:
A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.
Motion Estimation Using Bit-Wise Block Comparisons For Video Compresssion
US Patent:
7869516, Jan 11, 2011
Filed:
Mar 31, 2003
Appl. No.:
10/403864
Inventors:
Ruby B. Le - Princeton NJ, US
Dale Morris - Steamboat Springs CO, US
Dale Morris - Steamboat Springs CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H04N 7/12, H04N 11/02
US Classification:
37524016, 37524026
Abstract:
Motion estimation uses tally (Population Count) and XOR (or other bit-wise comparison) operations to obtain a block-match measure for reference and predicted blocks to identify motion vectors for use in video compression. The XOR operations can be performed on absolute or relative luminance data. For example, a one-bit-per-pixel representation of a block can indicate for each pixel its luminance relative to a local average luminance. The performance improvement offered by the invention (relative to methods using the absolute value of the differences of absolute luminance values) can more than offset a penalty in block-match accuracy due to loss of information in luminance data reduction and/or the ignoring of bit significance due to the bit-wise comparison.
Providing Hint Register Storage For A Processor
US Patent:
2013015, Jun 20, 2013
Filed:
Dec 20, 2011
Appl. No.:
13/330914
Inventors:
Dale Morris - Steamboat Springs CO, US
International Classification:
G06F 9/312
US Classification:
712220, 712E09033, 712E09023
Abstract:
In one embodiment, the present invention includes a method for receiving a data access instruction and obtaining an index into a data access hint register (DAHR) register file of a processor from the data access instruction, reading hint information from a register of the DAHR register file accessed using the index, and performing the data access instruction using the hint information. Other embodiments are described and claimed.
Purging Without Write-Back Of Cache Lines Containing Spent Data
US Patent:
8214601, Jul 3, 2012
Filed:
Jul 30, 2004
Appl. No.:
10/909057
Inventors:
Dale Morris - Steamboat Springs CO, US
Robert S. Schreiber - Palo Alto CA, US
Robert S. Schreiber - Palo Alto CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 12/00, G06F 13/00, G06F 13/28
US Classification:
711144, 711133, 711134, 711135, 711143, 711145
Abstract:
The present invention provides a system with a cache that indicates which, if any, of its sections contain data having spent status. The invention also provides a method for identifying cache sections containing data having spent status and then purging without writing back to main memory a cache line having at least one section containing data having spent status. The invention further provides a program that specifies a cache-line section containing data that is to acquire “spent” status. “Spent” data, herein, is useless modified or unmodified data that was formerly at least potentially useful data when it was written to a cache. “Purging” encompasses both invalidating and overwriting.
Computer System With Fabric Modules
US Patent:
2013010, May 2, 2013
Filed:
Sep 15, 2010
Appl. No.:
13/808507
Inventors:
Martin Goldstein - Campbell CA, US
Dale C. Morris - Steamboat Springs CO, US
Michael R. Krause - Boulder Creek CA, US
Dale C. Morris - Steamboat Springs CO, US
Michael R. Krause - Boulder Creek CA, US
International Classification:
H04L 12/56
US Classification:
370386
Abstract:
A chassis is configured to hold at least one horizontal row of node modules and a fabric module. The fabric module can be positioned above or below the row so that it can communicatively couple two or more node modules. Each of the node modules and the fabric modules can be inserted into and removed from the chassis longitudinally.
Out-Of-Order Processor Executing Speculative-Load Instructions
US Patent:
2004016, Aug 26, 2004
Filed:
Feb 21, 2003
Appl. No.:
10/371870
Inventors:
Dale Morris - Steamboat Springs CO, US
Matthew Reilly - Stow MA, US
Matthew Reilly - Stow MA, US
International Classification:
G06F009/00
US Classification:
712/225000
Abstract:
In addition to speculatively executing normal (non-speculative) load instructions in advance of their program order, an out-of-order processor executes the speculative (advanced) load instructions originally compiled for in-order processors. Both the speculative-load instructions and the corresponding check instructions can be executed out-of-order. The speculative-load instructions are treated like normal-load instructions while in the instruction queue. When a speculative-load instruction is retired from the instruction queue, it is transferred to a speculative load instruction manager. Execution of the corresponding check instruction can then check the validity of the speculative-load instruction.
Technique To Virtualize Processor Input/Output Resources
US Patent:
7849327, Dec 7, 2010
Filed:
Jan 19, 2005
Appl. No.:
11/040261
Inventors:
Hin L. Leung - San Jose CA, US
Kushagra V. Vaid - San Jose CA, US
Amy L. Santoni - Austin TX, US
Dale Morris - Steamboat Springs CO, US
Jonathan Ross - Woodinville WA, US
Kushagra V. Vaid - San Jose CA, US
Amy L. Santoni - Austin TX, US
Dale Morris - Steamboat Springs CO, US
Jonathan Ross - Woodinville WA, US
International Classification:
G06F 11/30, G06F 12/14
US Classification:
713189, 380287
Abstract:
A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.