COLYN SCOTT CASE
Pilots at Davis Hl Rd, Hyde Park, VT
License number
Vermont A0302462
Issued Date
Nov 2016
Expiration Date
Nov 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
345 Davis Hill Rd, Hyde Park, VT 05655
Professional information
Page Stream Sorter For Poor Locality Access Patterns
US Patent:
7664905, Feb 16, 2010
Filed:
Nov 3, 2006
Appl. No.:
11/592540
Inventors:
David A. Jarosh - Santa Clara CA, US
Sonny S. Yeoh - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
John H. Edmondson - Arlington MA, US
Sonny S. Yeoh - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
John H. Edmondson - Arlington MA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/14
US Classification:
711 5, 711154, 711158, 711165
Abstract:
In some applications, such as video motion compression processing for example, a request pattern or “stream” of requests for accesses to memory (e. g. , DRAM) may have, over a large number of requests, a relatively small number of requests to the same page. Due to the small number of requests to the same page, conventionally sorting to aggregate page hits may not be very effective. Reordering the stream can be used to “bury” or “hide” much of the necessary precharge/activate time, which can have a highly positive impact on overall throughput. For example, separating accesses to different rows of the same bank by at least a predetermined number of clocks can effectively hide the overhead involved in precharging/activating the rows.
Memory Management For Virtual Address Space With Translation Units Of Variable Range Size
US Patent:
7386697, Jun 10, 2008
Filed:
Mar 10, 2005
Appl. No.:
11/077662
Inventors:
Colyn S. Case - Hyde Park VT, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/08
US Classification:
711171, 711209, 710 9
Abstract:
In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.
Memory Management For Virtual Address Space With Translation Units Of Variable Range Size
US Patent:
7797510, Sep 14, 2010
Filed:
Apr 30, 2008
Appl. No.:
12/112602
Inventors:
Colyn S. Case - Hyde Park VT, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US
Gary D. Lorensen - San Jose CA, US
Sharon Rose Clay - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/08
US Classification:
711207, 345543
Abstract:
In a virtual memory system, address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. The clusters are dynamically created from a fragmented pool of physical addresses as new virtual address mappings are requested by consumers of the virtual memory space.
Memory Interface With Dynamic Selection Among Mirrored Storage Locations
US Patent:
8161252, Apr 17, 2012
Filed:
Nov 8, 2005
Appl. No.:
11/269975
Inventors:
Colyn S. Case - Hyde Park VT, US
Anders M. Kugler - Sunnyvale CA, US
Peter Tong - Cupertino CA, US
Anders M. Kugler - Sunnyvale CA, US
Peter Tong - Cupertino CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/00
US Classification:
711161, 711114, 711147, 711154, 711156
Abstract:
Devices and methods provide data from multiple storage locations to a processor. A data block containing data required by a processor is stored in two or more locations, e. g. , in a local memory and a system memory, both of which are accessible to the processor's memory interface. The memory interface directs each read request for mirrored data to one or another of the mirror locations. Selection of a mirror location to be read is based on substantially real-time information about which mirror location is best able to handle the request. For instance, the selection of a mirror location to access can be based at least in part on information about the level of activity on various buses that connect the processor to the mirror locations.
Shared Cache With Client-Specific Replacement Policy
US Patent:
7415575, Aug 19, 2008
Filed:
Dec 8, 2005
Appl. No.:
11/298256
Inventors:
Peter C. Tong - Cupertino CA, US
Colyn S. Case - Hyde Park VT, US
Colyn S. Case - Hyde Park VT, US
Assignee:
NVIDIA, Corporation - Santa Clara CA
International Classification:
G06F 12/12
US Classification:
711133, 711159, 711129
Abstract:
A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results from a request by the restricted client, the entry to be replaced is selected from a fixed subset of the cache entries. When a cache misses results from a request by any client other than the restricted client, any cache entry, including a restricted entry, can be selected to be replaced.
Raster Operations Unit With Interleaving Of Read And Write Requests Using Pci Express
US Patent:
8035647, Oct 11, 2011
Filed:
Aug 24, 2006
Appl. No.:
11/467132
Inventors:
Donald A. Bittel - San Jose CA, US
Paul MacDougal - Raleigh NC, US
Manas Mandal - Palo Alto CA, US
Colyn S. Case - Hyde Park VT, US
Paul MacDougal - Raleigh NC, US
Manas Mandal - Palo Alto CA, US
Colyn S. Case - Hyde Park VT, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G09G 5/39, G06F 13/14, G06F 13/00
US Classification:
345531, 345520, 345537
Abstract:
A raster operations (ROP) unit interleaves read and write requests for efficiently communicating with a frame buffer via a PCI Express (PCI E) link or other system bus that provides separate upstream and downstream data transfer paths. One example of a ROP unit processes pixels in groups, performing read modify writeback sequences for each group. The read requests associated with pixels in a second group are advantageously interleaved with the writeback requests for pixels in the first group prior to sending the requests on the system bus.
Asymmetrical Bus For Bus Link Width Optimization Of A Graphics System
US Patent:
7788439, Aug 31, 2010
Filed:
Oct 16, 2008
Appl. No.:
12/252525
Inventors:
William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
Colyn S. Case - Hyde Park VT, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/40
US Classification:
710307, 710 29
Abstract:
A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.
Control Device For Data Stream Optimizations In A Link Interface
US Patent:
7624221, Nov 24, 2009
Filed:
Jul 28, 2006
Appl. No.:
11/460960
Inventors:
Colyn S. Case - Hyde Park VT, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 13/40
US Classification:
710310, 710 18
Abstract:
Optimization logic that optimizes a stream of requests being transmitted onto a link by a link interface unit can be enabled or disabled based on a performance metric that represents a measure of the degree to which a response to a request is likely to be slowed due to congestion, propagation delays, or other bottlenecks in the system. For example, the performance metric can be based on a measured level of link activity due to requests from the transmitting device and/or a prediction as to behavior (e. g. , access time) of the target device that receives the stream of requests. The control logic advantageously does not require extra signals to be carried on the bus.
Dedicated Mechanism For Page Mapping In A Gpu
US Patent:
2008002, Jan 31, 2008
Filed:
Mar 21, 2007
Appl. No.:
11/689485
Inventors:
Peter C. Tong - Cupertino CA, US
Sonny S. Yeoh - San Jose CA, US
Kevin J. Kranzusch - Campbell CA, US
Gary D. Lorensen - San Jose CA, US
Kaymann L. Woo - Milpitas CA, US
Ashish Kishen Kaul - San Carlos CA, US
Colyn S. Case - Hyde Park VT, US
Stefan A. Gottschalk - Chapel Hill NC, US
Dennis K. Ma - Austin TX, US
Sonny S. Yeoh - San Jose CA, US
Kevin J. Kranzusch - Campbell CA, US
Gary D. Lorensen - San Jose CA, US
Kaymann L. Woo - Milpitas CA, US
Ashish Kishen Kaul - San Carlos CA, US
Colyn S. Case - Hyde Park VT, US
Stefan A. Gottschalk - Chapel Hill NC, US
Dennis K. Ma - Austin TX, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711207
Abstract:
Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.
Packet Combiner For A Packetized Bus With Dynamic Holdoff Time
US Patent:
7526593, Apr 28, 2009
Filed:
Oct 3, 2006
Appl. No.:
11/538399
Inventors:
Manas Mandal - Palo Alto CA, US
William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
Ashish Kishen Kaul - Santa Clara CA, US
William P. Tsu - San Jose CA, US
Colyn S. Case - Hyde Park VT, US
Ashish Kishen Kaul - Santa Clara CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 13/36, G06F 13/00
US Classification:
710310, 710 35, 370473, 370474, 370393, 370465
Abstract:
Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.