CHRISTOPHER WAYNE JONES
Pilots at 10 Ave, Portland, OR

7262621, Aug 28, 2007

Mar 21, 2005

11/084947

Aaron Joseph Caffee - Hillsboro OR, US
Christopher Scott Jones - Portland OR, US
Robert Beverly Lefferts - Portland OR, US
Ross Andrew Segelken - Portland OR, US
Jeffrey Lee Sonntag - Portland OR, US
Daniel Keith Weinlader - Allentown PA, US

Synopsys, Inc. - Mountain View CA

G01R 31/26

324763, 324765

A functional block under test (FBUT), comprising mixed-signal or analog circuits, can be tested by a digital test machine (DTM). A DTM sources test vectors to, and expects to receive certain vectors back from, a DUT. The DUT is a single, physically contiguous, IC upon which is integrated the FBUT, a mixed-signal generate and capture unit (MSGC) and a control system. The test vectors can include computer programs for instructing the control system on how to perform mixed-signal or analog-domain tests of the FBUT using resources of the MSGC (such as DACs and ADCs). The test vectors can also include data that effects the operation of a parameterized test procedure, where the test procedure is part of the control system. The control system, in accordance with the test procedure, uses the MSGC to perform mixed-signal or analog-domain tests of the FBUT. The FBUT can include an analog test bus.

2006021, Sep 28, 2006

Mar 24, 2005

11/090440

Chad Fogg - Hillsboro OR, US
Darrell Boggs - Aloha OR, US
Christopher Jones - Portland OR, US
Gary Brown - Aloha OR, US

G06F 9/44

712223000

A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an encoded immediate which specifies the shift count N. The processor corrects after the addition and shifting for an absent rounding bias added 2. The ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(A+B+C+D . . . +M+2) >>N

7586998, Sep 8, 2009

Nov 1, 2004

10/978610

Christopher Scott Jones - Portland OR, US
Jeffrey Lee Sonntag - Portland OR, US
John Theodore Stonick - Portland OR, US
Daniel Keith Weinlader - Allentown PA, US

Synopsys, Inc. - Mountain View CA

H04L 27/00

375316, 375346, 375348, 455 631, 455296

A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as D. Symbols located in the FIFO before Dare referred to as D. Symbols located in the FIFO after Dare referred to as D. Ddiffers from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dupon Dcan be measured, and thus any PR[k] measured, by measuring the average signal level of Dwhen only certain types of data streams occur in the FIFO.

2006021, Sep 28, 2006

Mar 24, 2005

11/090358

Darrell Boggs - Aloha OR, US
Chad Fogg - Hillsboro OR, US
Christopher Jones - Portland OR, US
Gary Brown - Aloha OR, US

G06F 9/30

712200000

A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified.

2006021, Sep 28, 2006

Mar 24, 2005

11/090441

Darrell Boggs - Aloha OR, US
Chad Fogg - Hillsboro OR, US
Christopher Jones - Portland OR, US
Gary Brown - Aloha OR, US

G06F 9/30

712218000

A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified. An ADDSRN instruction which performs addition and right shifting and rounding, in which one of the source operands is an immediate which specifies the shift count N and the processor derives a third added 2, and the ADDSRN instruction is used in accelerating digital signal processing code sequences of the form dest:=(+2)>>

7216220, May 8, 2007

Jul 14, 2004

10/891165

Gary L Brown - Aloha OR, US
Christopher S. Jones - Portland OR, US
Darrell D. Boggs - Aloha OR, US

Stexar Corp. - Beaverton OR

G06F 9/44

712242

A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

8503575, Aug 6, 2013

Jul 30, 2009

12/512736

Christopher Scott Jones - Portland OR, US
Jeffrey Lee Sonntag - Portland OR, US
John Theodore Stonick - Portland OR, US
Daniel Keith Weinlader - Allentown PA, US

Synopsys, Inc. - Mountain View CA

H04L 25/10

375317, 375316, 375346, 375348, 714709, 714699

A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as D. Symbols located in the FIFO before Dare referred to as D. Symbols located in the FIFO after Dare referred to as D. Ddiffers from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dupon Dcan be measured, and thus any PR[k] measured, by measuring the average signal level of Dwhen only certain types of data streams occur in the FIFO.

2006001, Jan 19, 2006

Jul 14, 2004

10/891166

Darrell Boggs - Aloha OR, US
Christopher Jones - Portland OR, US
Gary Brown - Aloha OR, US

G06F 9/00

712242000, 712245000

In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored customer code routine. The customer code routine thus behaves as a microcoded library routine.