CHRISTOPHER W READ, D.D.S.
Dentist at Katy Fwy, Houston, TX

5696954, Dec 9, 1997

Jun 7, 1995

8/486562

Karl M. Guttag - Sugar Land TX
Keith Balmer - Bedford, GB2
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Katy TX
Nicholas Ing-Simmons - Alconbury Weston, GB2
Philip Moyse - Bronham, GB2

Texas Instruments Incorporated - Dallas TX

G06F 1700

395562

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2. sup. N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

5761726, Jun 2, 1998

Jun 7, 1995

8/479981

Karl M. Guttag - Sugar Land TX
Keith Balmer - Bedford, GB2
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Katy TX
Nicholas Ing-Simmons - Huntingdon, GB2
Philip Moyse - Bronham, GB2

Texas Instruments Incorporated - Dallas TX

G06F 1200

711147

A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.

5606677, Feb 25, 1997

Jun 7, 1995

8/472828

Keith Balmer - Bedford, GB2
Christopher J. Read - Houston TX

Texas Instruments Incorporated - Dallas TX

G06F 744

395384

This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions.

5734880, Mar 31, 1998

Jun 7, 1995

8/480230

Karl M. Guttag - Missouri City TX
Keith Balmer - Bedford, GB2
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Kary TX
Nicholas Ing-Simmons - Huntingdon, GB2
Philip Moyse - Bedford, GB2

Texas Instruments Incorporated - Dallas TX

G06F 1500

395562

Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop.

5960193, Sep 28, 1999

Aug 27, 1997

8/922726

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX

Texas Instruments Incorporated - Dallas TX

G06F 900

395562

A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between corresponding numbers of the first and second sets. This difference is either added to or subtracted from a running sum based upon its sign. This is repeated for all number pairs. Preferably, the initial subtraction sets a status bit in a flag register (211) which controls the selection of addition or subtraction. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is preferably stored and later added to the running sum to recover the most significant overflow bits. This technique is preferably practiced using an arithmetic logic unit (230) that can be split into plural independent sections (301, 302, 303, 304). A multiple flags register (211) stores status bits of corresponding sections controlling the conditional addition to or subtraction from a like plurality of running sums.

6016538, Jan 18, 2000

Nov 30, 1993

8/160119

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX

Texas Instruments Incorporated - Dallas TX

G06F 1500

712 32

This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

5995748, Nov 30, 1999

Jun 19, 1998

9/099727

Karl M. Guttag - Missouri City TX
Keith Balmer - Bedford, GB
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Kary TX
Nicholas Ing-Simmons - Huntington, GB
Philip Moyse - Bedford, GB

Texas Instruments Incorporated - Dallas TX

G06F 9315

395562

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2. sup. N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer.

5272468, Dec 21, 1993

Apr 30, 1991

7/693506

Christopher J. Read - Houston TX

Texas Instruments Incorporated - Dallas TX

G09G 128

345153

A colorspace converter for use with image processing systems. The colorspace converter transforms digitized image data in one colorspace into image data in another colorspace, for use by a computer monitor. The colorspace converter uses look-up tables and other logic devices, and avoids the need for processor intervention. The look-up tables may be loaded for simple mapping, and extension look-up tables may be loaded for nonlinear extension transformations.

6032170, Feb 29, 2000

Apr 20, 1998

9/063318

Karl M. Guttag - Missouri City TX
Christopher J. Read - Houston TX
Keith Balmer - Bedford, GB

Texas Instruments Incorporated - Dallas TX

G06F 752, G06F 738

708620

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.