DR. CHRISTOPHER MICHAEL OLSON, D.C.
Chiropractic in Austin, TX

5957997, Sep 28, 1999

Apr 25, 1997

8/840926

Christopher H. Olson - Austin TX
Martin S. Schmookler - Austin TX

International Business Machines Corporation - Armonk NY

G06F 501

708205

A floating point result in a processor is efficiently normalized by predicting the mantissa shift required to normalize the result to an error of one bit position in one direction, resulting in minimum and maximum predicted shifts. Concurrently with an addition of operands to generate a result mantissa, an inversion of the minimum predicted shift is added to the operand exponent to generate an intermediate exponent corresponding to a maximum predicted shift. When the operand addition is complete, the result mantissa is partially shifted in response to the minimum predicted shift. The location of the leading one is then ascertained and compared to the remaining minimum predicted shift. If the minimum predicted shift is the actual shift required to normalize the result, the result mantissa is further shifted by the remaining minimum predicted shift and an exponent carry-in is asserted. On the other hand, if the maximum predicted shift is the actual shift required, the result mantissa is further shifted by the remaining minimum shift and by an additional bit position and the exponent carry-in is not asserted.

5822758, Oct 13, 1998

Sep 9, 1996

8/709793

Albert John Loper - Cedar Park TX
Timothy Alan Elliott - Austin TX
Christopher Hans Olson - Austin TX
David J. Shippy - Houston TX

International Business Machines Corporation - Armonk NY

G06F 1200

711130

A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event.

5241493, Aug 31, 1993

Dec 16, 1991

7/807697

Tan V. Chu - Austin TX
Faraydon O. Karim - Round Rock TX
Christopher H. Olson - Austin TX

International Business Machines Corporation - Armonk NY

G06F 738

364748

An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

2012029, Nov 15, 2012

Sep 8, 2011

13/228347

Christopher H. Olson - Austin TX, US
Manish K. Shah - Austin TX, US

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

G06F 9/38

712205, 712234, 712E09045

A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.

5961636, Oct 5, 1999

Sep 22, 1997

8/934960

Jeffrey Scott Brooks - Round Rock TX
Hoichi Cheong - Austin TX
Tiberiu Carol Galambos - Haifa, IL
Christopher Hans Olson - Austin TX

International Business Machines Corporation - Armonk NY

G06F 9302

712228

In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.

8078942, Dec 13, 2011

Sep 4, 2007

11/849749

Paul J. Jordan - Austin TX, US
Christopher H. Olson - Austin TX, US

Oracle America, Inc. - Redwood City CA

G11C 29/00, H03M 13/00

714773, 714764

In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.

8438208, May 7, 2013

Jun 19, 2009

12/488372

Christopher H. Olson - Austin TX, US
Jeffrey S. Brooks - Austin TX, US
Robert T. Golla - Round Rock TX, US
Paul J. Jordan - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 7/52, G06F 7/38

708625, 708490, 708501, 708503, 708523, 708620

A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.

7478225, Jan 13, 2009

Jun 30, 2004

10/881071

Jeffrey S. Brooks - Austin TX, US
Christopher H. Olson - Austin TX, US
Robert T. Golla - Round Rock TX, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 9/30

712214

An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. The processor may also include first and second execution units respectively configured to execute shorter-latency and longer-latency instructions and to respectively write shorter-latency or longer-latency instruction results to a result write port during a first or second writeback stage. The first writeback stage may occur a fewer number of cycles after instruction issue than the second writeback stage. The instruction fetch logic may be further configured to guarantee result write port access by the second execution unit during the second writeback stage by preventing the shorter-latency instruction from issuing during a cycle for which the first writeback stage collides with the second writeback stage.

7620821, Nov 17, 2009

Feb 24, 2005

11/064595

Gregory F. Grohoski - Austin TX, US
Christopher H. Olson - Austin TX, US
Leonard D. Rarick - Los Altos CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 11/30

713189, 713172, 713184, 713193, 380 37, 380 1, 380 28, 380277, 726 22, 726 3

A processor including general-purpose and cryptographic functionality, in which cryptographic operations are visible to user-specified software. According to one embodiment, a processor may include instruction execution logic configured to execute instructions specified by a user of the processor, where the instructions are compliant with a general-purpose instruction set architecture. The processor may further include a cryptographic functional unit configured to implement a plurality of cryptographic operations, and further configured to process the cryptographic operations independently of the instruction execution logic. A subset of the instructions may be executable to cause individual ones of the cryptographic operations to be processed by the cryptographic functional unit.