CHRISTOPHER EDWARD KOOB
Pilots at Merion Cv, Round Rock, TX

2013030, Nov 14, 2013

May 8, 2012

13/466359

Christopher Edward Koob - Round Rock TX, US
Ajay Anant Ingle - Austin TX, US
Lucian Codrescu - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 12/08

711129, 711E12038

Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

7809783, Oct 5, 2010

Feb 15, 2006

11/355397

Shankar Krithivasan - Austin TX, US
Christopher Edward Koob - Round Rock TX, US

QUALCOMM Incorporated - San Diego CA

G06F 7/52

708628

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e. g. , CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e. g. , radix-4) Booth recoding on B generates “n” multiplication factors, where “n,” an integer, is approximating one half of the number of the multiplier bits. “n” partial products are generated using the “n” multiplication factors as multipliers of A. Then, a multiplication tree is formed using radix-m Booth encoding. The multiplication tree includes multiplier bits associated to generate a multiplication factors. In the event of a negative multiplication factor, a two's complement of A is formed by inverting the bits of A and associating a sticky “1” to complete the two's complementation. Furthermore, multiplication factors are reduced in multiple stages to a form sum and carry components of a pre-determined length. The additive inverse of A×B is formed by using novel techniques to calculate the product of A and −B.

7797366, Sep 14, 2010

Feb 15, 2006

11/356359

Shankar Krithivasan - Austin TX, US
Christopher Edward Koob - Round Rock TX, US
William C. Anderson - Austin TX, US

QUALCOMM Incorporated - San Diego CA

G06F 7/52

708628, 708629

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e. g. , code division multiple access) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree.

2013028, Oct 24, 2013

Apr 18, 2012

13/449833

Christopher Edward Koob - Round Rock TX, US
Dana M. Vantrease - Austin TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 12/08

711141, 711E12017

Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to reduce stalls during write operations. The WDI state is a dataless state with guaranteed write permissions. When a first processor of the multiprocessor system makes a write request for a first cache entry of a first cache, the WDI state associated with the first cache entry includes write permissions for the write to directly proceed to one or more higher levels of memory in the shared memory, such that delays associated with obtaining write permissions is reduced at the first cache. The WDI state is treated as an invalid state for a read request to the first cache entry by the first processor.

8266409, Sep 11, 2012

Mar 3, 2009

12/397185

Christopher Edward Koob - Round Rock TX, US
Ajay Anant Ingle - Austin TX, US
Lucian Codrescu - Austin TX, US
Jian Shen - Austin TX, US

QUALCOMM Incorporated - San Diego CA

G06F 12/00, G06F 13/00, G06F 13/28, G06F 9/26, G06F 9/34

711212, 711118, 711172, 711202

In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.

8341353, Dec 25, 2012

Jan 14, 2010

12/687552

Suresh K. Venkumahanti - Austin TX, US
Christopher Edward Koob - Round Rock TX, US
Lucian Codrescu - Austin TX, US

QUALCOMM Incorporated - San Diego CA

G06F 12/08

711122, 711120, 711E12042, 711E12043

A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.

2009032, Dec 31, 2009

Jun 26, 2008

12/146657

Ajay Anant Ingle - Austin TX, US
Christopher Edward Koob - Round Rock TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 12/10

711207, 711E12061

A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.

2011012, May 26, 2011

Nov 20, 2009

12/622998

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Mao Zeng - Austin TX, US
Christopher Edward Koob - Round Rock TX, US
Charles Joseph Tabony - Austin TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 9/30, G06F 9/302

712208, 712221, 712E09016, 712E09017

A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.

7801164, Sep 21, 2010

Apr 27, 2006

11/412917

Christopher Koob - Round Rock TX, US
Ali A. Poursepanj - Austin TX, US
David P. Sonnier - Austin TX, US

Agere Systems Inc. - Allentown PA

H04L 12/56

370412

Improved timeout table mechanism are disclosed. By way of example, a method for providing timeout delays for data queues in a processing system includes the following steps. A timeout structure is maintained. The timeout structure includes two or more groups, each group including two or more bins, each bin having a range of timeout delay values associated therewith, each group having a weight associated therewith, the weight of each group being based on a rate and a quantity of queues assignable to each group. A timeout delay value to be assigned to a data queue in the processing system is selected.

2012026, Oct 18, 2012

Jun 25, 2012

13/531803

Christopher Edward Koob - Round Rock TX, US
Ajay Anant Ingle - Austin TX, US
Lucian Codrescu - Austin TX, US
Jian Shen - Austin TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 12/08

711144, 711E12037

A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.