CHRISTOPHER ATLEE BLAIR
Pilots at 86 Ave Ct, Puyallup, WA
License number
Washington A4731730
Issued Date
Jan 2012
Expiration Date
Jan 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
2121 86Th Avenue Ct E, Puyallup, WA 98371
Professional information
Reducing Base Resistance Of A Bjt By Forming A Self Aligned Silicide In The Single Crystal Region Of The Extrinsic Base
US Patent:
5139961, Aug 18, 1992
Filed:
Apr 2, 1990
Appl. No.:
7/503498
Inventors:
Alan G. Solheim - Puyallup WA
Bamdad Bastani - Danville CA
James L. Bouknight - Puyallup WA
George E. Ganschow - Trabuco Canyon CA
Bancherd Delong - Puyallup WA
Rajeeva Lahri - Puyallup WA
Steve M. Leibiger - Graham WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Madan Biswal - Puyallup WA
Tad Davies - Puyallup WA
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Bamdad Bastani - Danville CA
James L. Bouknight - Puyallup WA
George E. Ganschow - Trabuco Canyon CA
Bancherd Delong - Puyallup WA
Rajeeva Lahri - Puyallup WA
Steve M. Leibiger - Graham WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Madan Biswal - Puyallup WA
Tad Davies - Puyallup WA
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2133
US Classification:
437 33
Abstract:
A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.
Method Of Fabricating Bicmos Device
US Patent:
5661046, Aug 26, 1997
Filed:
Aug 4, 1994
Appl. No.:
8/285839
Inventors:
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
US Classification:
438202
Abstract:
A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.
Method Of Fabricating Bicmos Device
US Patent:
5338694, Aug 16, 1994
Filed:
Mar 9, 1992
Appl. No.:
7/847876
Inventors:
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
US Classification:
437 31
Abstract:
A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.
High Performance Semiconductor Devices And Their Manufacture
US Patent:
5242854, Sep 7, 1993
Filed:
May 7, 1992
Appl. No.:
7/879650
Inventors:
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Christopher S. Blair - Puyallup WA
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21302, H01L 2176
US Classification:
437 69
Abstract:
A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.
Self-Aligned Silicided Base Bipolar Transistor And Resistor And Method Of Fabrication
US Patent:
5045483, Sep 3, 1991
Filed:
Apr 2, 1990
Appl. No.:
7/503340
Inventors:
Bancherd DeLong - Puyallup WA
Christopher S. Blair - Puyallup WA
George E. Ganschow - Puyallup WA
Thomas S. Crabb - Puyallup WA
Christopher S. Blair - Puyallup WA
George E. Ganschow - Puyallup WA
Thomas S. Crabb - Puyallup WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21328
US Classification:
437 31
Abstract:
A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.
Method Of Fabricating Bicmos Device
US Patent:
5338696, Aug 16, 1994
Filed:
Mar 1, 1993
Appl. No.:
8/022708
Inventors:
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Alan G. Solheim - Puyallup WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Rajeeva Lahri - Puyallup WA
Madan Biswal - Puyallup WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
US Classification:
437 34
Abstract:
A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.