Position:
IC Layout Engineer (Consultant) at Qualcomm Inc.
Work:
Qualcomm Inc.
- Greater San Diego Area since Apr 2013
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IC Layout Engineer (Consultant)
Cadence Design Systems
- United States Jan 2011 - Mar 2013
-
Custom - IC Lead Applications Engineer
ON Semiconductor
- United States Mar 2008 - Jan 2011
-
Sr. IC Mask Designer
AMI Semiconductor
Aug 2002 - Feb 2008
-
Sr. IC Mask Designer
ACH Distributing
Feb 2000 - Jan 2002
-
Owner
Education:
Utah Valley University 2001 - 2004
AAS - IC Layout Design, IC Mask Layout
Skills:
Mixed Signal, IC, EDA, Cadence, Layout, Floorplanning, Physical Design, Analog, LVS, DRC, Physical Verification, BiCMOS, PLL, CMOS, Latch-up, Virtuoso XL, Virtuoso Layout, Schematic Editor, Crosstalk, Cadence Skill, CDF, Assura, Dracula, Tanner, L-Edit, Tanner Tools, Calibre, RC Extraction, Matching, RF, BJT, Circuit Design, Virtuoso, Cadence Virtuoso, ASIC, IC layout, Power Management, Integrated Circuit Design, Low-power Design, Semiconductors, VCO, Parasitic Extraction, Semiconductor Industry, Debugging, DAC, Cadence Virtuoso XL, ESD control, LNA, ERC, PVS
Interests:
IC Layout/Mask design flow and matching improvements, App. Development with C# .net, SKILL Pcell development, Tcell development, reading, writing, fishing, tennis, golf and FPS games. Family is a central in my life.