CHRIS E MCCARTY
Nursing at San Paulo Cir, Melbourne, FL

6441447, Aug 27, 2002

Aug 11, 1999

09/367325

Joseph A. Czagas - Palm Bay FL
George Bajor - Melbourne FL
Leonel Enriquez - Melbourne FL
Chris A. McCarty - Melbourne FL

Intersil Corporation - Palm Bay FL

H01L 2976

257379, 257536, 257537, 257766, 257904

A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

5270265, Dec 14, 1993

Sep 1, 1992

7/939115

Donald F. Hemmenway - Melbourne FL
Stephen J. Gaul - Melbourne FL
Chris A. McCarty - Melbourne FL

Harris Corporation - Melbourne FL

H01L 21465

437228

Creation of structural defects in a trench-isolated island structure is obviated by protecting the bottom of the trench pattern during etching of the hard mask surface oxide. A layer of photoresist is non-selectively deposited on the hard mask oxide layer and in the trench pattern, so that the photoresist buffer layer fills the trench pattern and is formed atop the hard mask oxide layer. The deposited photoresist is controllably flood-irradiated, so as to expose the irradiated photoresist down to a depth in the trench pattern that is at or somewhat deeper than the surface of the hard mask insulating material. The exposed photoresist is then developed, so as to remove the irradiated depth portion of the photoresist lying atop the hard mask oxide layer and partially extending into the trench, thus exposing the hard mask oxide layer, but leaving a sufficient quantity of unexposed photoresist in the trench pattern that provides a surface barrier for the underlying oxide. A wet etch is then non-selectively applied to the hard mask oxide layer, so as to completely remove the hard mask oxide layer from the top surface of the semiconductor islands. Because of the barrier in the bottom of the trench pattern, the oxide etch does not attack the underlying oxide.

7224074, May 29, 2007

Dec 19, 2005

11/305987

John T Gasner - Satellite Beach FL, US
Michael D Church - Sebastian FL, US
Sameer D Parab - Fremont CA, US
David A Decrosta - Melbourne FL, US
Robert Lomenic - Palm Bay FL, US
Chris A McCarty - Melbourne FL, US

Intersil Americas Inc. - Milpitas CA

H01L 23/48, H01L 21/44

257779, 257780, 257786, 438612, 438614

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

7005369, Feb 28, 2006

Oct 31, 2003

10/698184

John T. Gasner - Satellite Beach FL, US
Michael D. Church - Sebastian FL, US
Sameer D. Parab - Fremont CA, US
David A. Decrosta - Melbourne FL, US
Robert L. Lomenick - Palm Bay FL, US
Chris A. McCarty - Melbourne FL, US

Intersil American Inc. - Milpitas CA

H01L 21/44

438614, 438618, 438622, 438624, 438625, 438652

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

2003000, Jan 9, 2003

Apr 3, 2002

10/117378

Ravi Chawla - Atlanta GA, US
William Eisenstadt - Gainesville FL, US
Robert Fox - Gainesville FL, US
Don Hemmenway - Melbourne FL, US
Jeffrey Johnston - Indian Harbour Beach FL, US
Chris McCarty - Melbourne FL, US

University of Florida - Gainesville FL

H01L023/58

257/048000

A semiconductor test system includes at least one semiconductor wafer having working dies and at least one test die formed therein. Each of the working dies includes at least one bipolar transistor. A tester selectively supplies a changing direct current (DC) input signal to a selected test die and monitors a DC output signal therefrom. Each test die includes a test oscillator having at least one sample bipolar transistor substantially identical to the bipolar transistors of the working dies. The test oscillator switches between a non-oscillating state and an oscillating state as the DC input signal changes, and generates the DC output signal to the tester indicative of switching between the non-oscillating state and the oscillating state. A threshold level of a bias current that causes the test oscillator to switch between the non-oscillating state and the oscillating state is correlated to the maximum oscillation frequency and the transition frequency of the sample bipolar transistor.

7795130, Sep 14, 2010

Apr 19, 2007

11/737392

John T. Gasner - Satellite Beach FL, US
Michael D. Church - Sebastian FL, US
Sameer D. Parab - Fremont CA, US
David A. Decrosta - Melbourne FL, US
Robert Lomenick - Palm Bay FL, US
Chris A. McCarty - Melbourne FL, US

Intersil Americas Inc. - Milipitas CA

H01L 21/44

438614, 438618, 438622, 438624, 257779, 257E23019, 257E2302

A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

8274160, Sep 25, 2012

Jun 28, 2010

12/825030

John T. Gasner - Satellite Beach FL, US
Michael D. Church - Sebastian FL, US
Sameer D. Parab - Fremont CA, US
David A. Decrosta - Melbourne FL, US
Robert Lomenick - Palm Bay FL, US
Chris A. McCarty - Melbourne FL, US

Intersil Americas Inc. - Milpitas CA

H01L 23/52, H01L 29/40, H01L 21/44

257779, 257E23019, 257E2302, 257E2159, 438614, 438618, 438622

A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

8569896, Oct 29, 2013

Jun 26, 2012

13/532843

John T. Gasner - Satellite Beach FL, US
Michael D. Church - Canyon Lake FL, US
Sameer D. Parab - Fremont CA, US
David A. Decrosta - Melbourne FL, US
Robert Lomenick - Palm Bay FL, US
Chris A. McCarty - Melbourne FL, US

Intersil Americas Inc. - Milpitas CA

H01L 23/48, H01L 21/44

257779, 257780, 257786, 438612, 438614

A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

4553315, Nov 19, 1985

Apr 5, 1984

6/597060

Chris McCarty - Melbourne FL

Harris Corporation - Melbourne FL

H01L 21265, H01L 2128

29571

The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.