CHIRAG K PATEL
Engineering in Methuen, MA

License number
Massachusetts 17763
Issued Date
Nov 1, 1997
Type
Engineer in Training
Address
Address
Methuen, MA 01844

Professional information

Chirag Patel Photo 1

Method, Article, And Apparatus For Dynamic Phase Delay Compensator

US Patent:
2009020, Aug 13, 2009
Filed:
Apr 22, 2009
Appl. No.:
12/428162
Inventors:
David DOYLE - Quincy MA, US
Hossain HAJIMOWLANA - Merrimack NH, US
Kevin GAGNE - Hampstead NH, US
Joseph BASTOS - Burlington MA, US
Chirag PATEL - Methuen MA, US
Assignee:
ANALOG DEVICES, INC. - Norwood MA
International Classification:
H04L 7/00
US Classification:
375355
Abstract:
An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.


Chirag Patel Photo 2

Method, Article, And Apparatus For A Dynamic Phase Delay Compensator

US Patent:
7526054, Apr 28, 2009
Filed:
Mar 4, 2005
Appl. No.:
11/072562
Inventors:
David Doyle - Quincy MA, US
Hossain Hajimowlana - Merrimack NH, US
Kevin Gagne - Hampstead NH, US
Joseph Bastos - Burlington MA, US
Chirag Patel - Methuen MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H04L 7/00
US Classification:
375355, 375376, 375364, 375219, 370505, 370503, 710100, 710306
Abstract:
An apparatus, method, and article to dynamically adjust a data signal using a regenerated clock signal in an emulator to increase communication speed between the emulator and the evaluation board is disclosed. In one embodiment, this is achieved by applying a reference clock signal at a predetermined frequency to a digital circuit. A delayed return data signal is then sampled from the digital circuit. The sampled delayed return data signal is then compared to an expected return data signal. The delayed return data signal is then adjusted as a function of the comparison to increase the communication speed between the emulator and the evaluation board.