CHENG IH WU
Engineering in San Jose, CA
License number
Massachusetts 28753
Expiration Date
Jun 30, 1984
Type
Mechanical Engineer
Address
Address
San Jose, CA 95120
Professional information
Eprom Fabrication Process
US Patent:
4830974, May 16, 1989
Filed:
Jan 11, 1988
Appl. No.:
7/142641
Inventors:
Chung-Chen Chang - Los Altos CA
Cheng C. Wu - San Jose CA
Cheng C. Wu - San Jose CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H01L 2996
US Classification:
437034
Abstract:
An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500. ANG. thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600. ANG. , removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100. degree. -1200. degree. C. over both the substrate and first polysilicon layer, depositing a second polysilicon gate layer and selectively etching away the layers to form first the device gates and second memory all gate from the second polysilicon layer, and then the floating gate from the first polysilicon layer using the second gate as a self-aligning mask. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass and intermetal layers by means of glass reflow and planarization and wet/dry etching of the intermetal layer.