Charles Willard Moore
Architects at Quarry Rd, Austin, TX

6678820, Jan 13, 2004

Mar 30, 2000

09/538993

James Allan Kahle - Austin TX
Charles Roberts Moore - Austin TX

International Business Machines Corporation - Armonk NY

G06F 900

712239, 712241

A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and a plurality of branch prediction circuits including a lock acquisition branch prediction circuit that predicts a speculative execution path for a conditional branch instruction. The processor further includes a selector that selects the speculative execution path predicted by the lock acquisition branch prediction circuit in response to an indication that the conditional branch instruction is dependent upon lock acquisition. In a preferred embodiment, the indication that the conditional branch instruction is dependent upon lock acquisition is encoded within the conditional branch instruction.

6766442, Jul 20, 2004

Mar 30, 2000

09/538992

James Allan Kahle - Austin TX
Charles Roberts Moore - Austin TX

International Business Machines Corporation - Armonk NY

G06F 900

712239, 712233

A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions, a condition register, and a branch prediction circuit that predicts a condition register-dependent branch instruction by reference to a potentially stale condition register value to produce a speculative instruction fetch address. In a preferred embodiment, the processor includes branch execution circuitry that subsequently determines if the speculative instruction fetch address is correct by reference to a non-stale value of the condition register.

6662294, Dec 9, 2003

Sep 28, 2000

09/671868

James Allan Kahle - Austin TX
Charles Roberts Moore - Austin TX

International Business Machines Corporation - Armonk NY

G06F 938

712226, 712234

A microprocessor and method of processing instructions therein are disclosed. Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence within the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor. Detecting the short branch sequence may include calculating the relative branch address associated with the conditional branch instruction and comparing the relative branch address to a specified maximum.

5442766, Aug 15, 1995

Oct 9, 1992

7/959194

Tan V. Chu - Austin TX
Charles R. Moore - Austin TX
John S. Muhich - Austin TX
Terence M. Potter - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1210, G06F 938, G06F 1212, G06F 1208

395414

A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit. A translation object within the translation array is preferably replaced each time the fetcher unit fails to translate an effective address into a real address by replacing the least recently utilized (LRU) translation object with a newly determined translation object.

5437017, Jul 25, 1995

Oct 9, 1992

7/959189

Charles R. Moore - Austin TX
John S. Muhich - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1208

395400

Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system.

6938148, Aug 30, 2005

Dec 15, 2000

09/737342

Charles Roberts Moore - Austin TX, US
Ravi Nair - Briarcliff Manor NY, US
Wolfram M. Sauer - Nufringen, DE

International Business Machines Corporation - Armonk NY

G06F015/00

712216

A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.

2002015, Oct 24, 2002

Apr 19, 2001

09/838461

Richard Eickemeyer - Rochester MN, US
Harm Hofstee - Austin TX, US
Charles Moore - Austin TX, US
Ravi Nair - Briarcliff Monor NY, US

International Business Machines Corporation - Armonk NY

G06F009/00

712/228000

A mixed-mode multithreading processor is provided. In one embodiment, the multi-mode multithreading processor includes a multithreaded register file with a plurality of registers, a thread control unit, and a plurality of hold latches. Each of the hold latches and registers stores data representing a first instruction thread and a second instruction thread. The thread control unit provides thread control signals to each of the hold latches and registers selecting a thread using the data. The thread control unit provides control signals for interleaving multithreading except when a long latency operation is detected in one of the threads. During a predetermined period corresponding approximately to the duration of the long latency operation, the thread control unit places the processor in a mode in which only instructions corresponding to the other thread are read out of the hold latches and registers. Once the predetermined period of time has expired, the processor returns to interleaving multithreading.

5611058, Mar 11, 1997

Mar 20, 1996

8/619100

Charles R. Moore - Austin TX
John S. Muhich - Austin TX
Robert J. Reese - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1314, G06F 1318, G06F 1338

395309

A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

4916658, Apr 10, 1990

Dec 18, 1987

7/135170

Charles R. Moore - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1314

364900

A buffer for storing data words consisting of several storage locations together with circuitry providing a first indicator that designates the next storage location to be stored into, a second indicator designating the next storage location to be retrieved from, and circuitry that provides the number of locations available for storage and the number of locations available for retrieval. Furthermore, the buffer includes the capability to store and retrieve several data words simultaneously.