CHARLES R COOK
Medical Practice at 39 Way, West Palm Beach, FL

License number
Florida 509269
Issued Date
Mar 14, 2005
Effective Date
Jun 17, 2009
Expiration Date
Dec 1, 2008
Category
Health Care
Type
Emergency Medical Technician
Address
Address
3903 39Th Way, West Palm Beach, FL 33407

Personal information

See more information about CHARLES R COOK at radaris.com
Name
Address
Phone
Charles Cook, age 89
4 Crossleaf Ct E, Palm Coast, FL 32137
Charles Cook
4866 Hickory Shores Blvd, Gulf Breeze, FL 32563
Charles Cook, age 61
4950 NW 70Th St, Chiefland, FL 32626
(352) 455-9430
Charles Cook
4961 Banana Ave, Cocoa, FL 32926
(321) 504-0864
Charles Cook
5105 Flamingo Dr, Pensacola, FL 32507
(850) 492-5955

Organization information

See more information about CHARLES R COOK at bizstanding.com

Charles R. Cook Company

618 Us Hwy 1, West Palm Beach, FL 33408

Status:
Inactive
Registration:
Dec 21, 1992
State ID:
P92000013189
Business type:
Domestic for Profit Corporation
Director:
Charles R. Cook Director, inactive

Professional information

See more information about CHARLES R COOK at trustoria.com
Charles Cook Photo 1
Method For Providing Electrical Isolating Material In Selected Regions Of A Semiconductive Material

Method For Providing Electrical Isolating Material In Selected Regions Of A Semiconductive Material

US Patent:
4056415, Nov 1, 1977
Filed:
Jul 15, 1976
Appl. No.:
5/705632
Inventors:
Charles R. Cook - North Palm Beach FL
Aung San U - West Palm Beach FL
Raymond E. Scherrer - West Palm Beach FL
Assignee:
International Telephone and Telegraph Corporation - Nutley NJ
International Classification:
H01L 2120
US Classification:
148187
Abstract:
An integrated circuit having dielectric isolation is fabricated by growing a double epitaxial layer of N-type semiconductive material onto a P-type substrate. A dielectric layer is formed over the epitaxial layer and thereafter the dielectric and a portion of the epitaxial growth are removed in selected isolation regions to expose the semiconductive material. A dielectric is formed by anodizing the N-type semiconductive material in the selected isolation regions to provide electrical isolation between the remaining portions of the epitaxial growth. Base and emitter elements are formed in the conventional manner to complete the integrated circuit which is thereafter packaged.


Charles Cook Photo 2
Method For Providing Electrical Isolating Material In Selected Regions Of A Semiconductive Material And The Product Produced Thereby

Method For Providing Electrical Isolating Material In Selected Regions Of A Semiconductive Material And The Product Produced Thereby

US Patent:
4005452, Jan 25, 1977
Filed:
Nov 15, 1974
Appl. No.:
5/524296
Inventors:
Charles R. Cook - North Palm Beach FL
Assignee:
International Telephone and Telegraph Corporation - Nutley NJ
International Classification:
H01L 2712
US Classification:
357 49
Abstract:
An integrated circuit having dielectric isolation is fabricated by growing a double epitaxial layer of N-type semiconductive material onto a P-type substrate. A dielectric layer is formed over the epitaxial layer and thereafter the dielectric and the epitaxial growth are removed in selected isolation regions to expose the substrate. A metal layer is evaporated onto the device so that metal is deposited both on the exposed substrate material and on the dielectric layer. A dielectric is formed by selectively anodizing the metal deposited on the exposed substrate to provide electrical isolation between the remaining portions of the epitaxial growth. Because of the electrical insulating characteristics of the dielectric layer, the metal deposited on the dielectric layer is not anodized and may be removed using a compound that attacks the unanodized metal and has little effect on the anodized metal. Base and emitter elements are formed in the conventional manner to complete the integrated circuit.


Charles Cook Photo 3
Semiconductor Device Having Porous Anodized Aluminum Isolation Between Elements Thereof

Semiconductor Device Having Porous Anodized Aluminum Isolation Between Elements Thereof

US Patent:
4081823, Mar 28, 1978
Filed:
Jun 23, 1976
Appl. No.:
5/699000
Inventors:
Charles R. Cook - North Palm Beach FL
Assignee:
International Telephone and Telegraph Corporation - Nutley NJ
International Classification:
H01L 2702, H01L 2712, H01L 2704
US Classification:
357 47
Abstract:
An integrated circuit having dielectric isolation is fabricated by growing a double epitaxial layer of N-type semiconductive material onto a P-type substrate. A dielectric layer is formed over the epitaxial layer and thereafter the dielectric and the epitaxial growth are removed in selected isolation regions to expose the substrate. A metal layer is evaporated onto the device so that metal is deposited both on the exposed substrate material and on the dielectric layer. A dielectric is formed by selectively anodizing the metal deposited on the exposed substrate to provide electrical isolation between the remaining portions of the epitaxial growth. Because of the electrical insulating characteristics of the dielectric layer, the metal deposited on the dielectric layer is not anodized and may be removed using a compound that attacks the unanodized metal and has little effect on the anodized metal. Base and emitter elements are formed in the conventional manner to complete the integrated circuit.


Charles Cook Photo 4
Self-Aligning Package For Integrated Circuits

Self-Aligning Package For Integrated Circuits

US Patent:
4056681, Nov 1, 1977
Filed:
Aug 4, 1975
Appl. No.:
5/601854
Inventors:
Charles R. Cook - North Palm Beach FL
Assignee:
International Telephone and Telegraph Corporation - Nutley NJ
International Classification:
H05K 500
US Classification:
174 52FP
Abstract:
A self-aligning integrated circuit package includes an integrated circuit die having raised contact pads mounted to an interconnecting die in flip chip fashion. The interconnecting die is formed of anodizable material and has raised anodized portions that form guide means for aligning the integrated circuit die and the leads of a lead frame so that they are positioned over conductive portions of the interconnecting die which connect the contact pads of the integrated circuit to the leads of the lead frame.


Charles Cook Photo 5
Semiconductor Scribing Method

Semiconductor Scribing Method

US Patent:
4096619, Jun 27, 1978
Filed:
Jan 31, 1977
Appl. No.:
5/764095
Inventors:
Charles R. Cook - North Palm Beach FL
Assignee:
International Telephone & Telegraph Corporation - Nutley NJ
International Classification:
B23P 1700
US Classification:
29413
Abstract:
This relates to the scribing and breaking of a semiconductor wafer into individual dies by anodizing the silicon in regions corresponding to the die boundaries. The regions are selectively anodized, and the anodization is continued until the anodized silicon extends into the semiconductor wafer to a depth that allows easy breakage when the wafer is stressed. To facilitate breakage, the anodized silicon may be removed with hydrofluoric acid.