CHARLES ALLEN JOHNSON
Pilots in Rochester, MN

6260164, Jul 10, 2001

Jul 31, 1998

9/127355

Anthony Gus Aipperspach - Rochester MN
Leland Leslie Day - Rochester MN
Paul Allen Ganfield - Rochester MN
Charles Luther Johnson - Rochester MN

International Business Machines Corporation - Armonk NY

G01R 3128, G06F 104

714726

A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

6928314, Aug 9, 2005

Jan 23, 1998

09/355075

Charles D. Johnson - Rochester MN, US
Judd E. Reed - Rochester MN, US

Mayo Foundation for Medical Education and Research - Rochester MN

A61B005/05

600407, 128920, 382128

This invention is a system, method, and article of manufacture for imaging tubular structures of the human body, such as the digestive tract of a living person, with a medical imaging device such as a computed tomography (CT) scanner and a computer work station. The system comprises receiving a first image data set representative of a portion of the colon in a prone position and a second image data set representative of a portion of the colon in a supine position, at a series of viewpoints. At each of the viewpoints, an image is generated of the colon in the prone and supine positions. The prone and supine images of the colon are simultaneously displayed on a screen display in a dual view mode.

5891030, Apr 6, 1999

Jan 24, 1997

8/787286

Charles Daniel Johnson - Rochester MN
Amy Kiyo Hara - Rochester MN
Judd Evon Reed - Rochester MN

Mayo Foundation for Medical Education and Research - Rochester MN

A61B 0500

600407

A system, method, and article of manufacture for imaging tubular structures of the human body, such as the digestive tract of a living person, with a medical imaging device such as a computed tomography (CT) scanner and a computer workstation. The CT scanner is used to generate cross-sectional axial images of a human colon which are then transferred to the computer workstation. A colon midline is defined which follows the colon lumen. The computer workstation supports colon midline definition by generating and displaying reformatted cross-sectional images, volume rendered scouts, and interluminal views. Semi-automatic midline defining tools are also included. After the midline is defined, a montage of images is displayed for diagnostic purposes. The images include axial sections, transluminal cross section, and intraluminal volume rendered images.

2012019, Aug 2, 2012

Mar 16, 2012

13/422566

Gerald K. Bartley - Rochester MN, US
Russell Dean Hoover - Rochester MN, US
Charles Luther Johnson - Rochester MN, US
Steven Paul VanderWiel - Rosemount MN, US
Patrick Ronald Varekamp - Croton on Hudson NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 17/50

716122, 716129

An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

2014007, Mar 13, 2014

Sep 13, 2012

13/613564

Gerald K. Bartley - Rochester MN, US
Charles L. Johnson - Rochester MN, US
Joseph Kuczynski - Rochester MN, US
David R. Motschman - Rochester MN, US
Arvind K. Sinha - Rochester MN, US
Kevin A. Splittstoesser - Stewartville MN, US
Timothy J. Tofil - Rochester MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 23/367, H01L 21/02, H01L 23/00

257690, 438122, 264108, 264437

The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip

5235521, Aug 10, 1993

Oct 8, 1991

7/773061

Charles L. Johnson - Rochester MN
Robert F. Lembach - Rochester MN
Bruce G. Rudolph - Rochester MN
Robert R. Williams - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 1560

364489

In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

5815694, Sep 29, 1998

Dec 21, 1995

8/576172

Paul Allen Ganfield - Rochester MN
Charles Luther Johnson - Rochester MN
James David Strom - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 108

395556

An apparatus and method for providing a variable frequency clock source is described wherein the frequency may be changed while maintaining the phase of the clock signal. A frequency conversation circuit, such as a phase locked loop (PLL), is employed to change the frequency of the clock and is controlled by a control unit which maintains the phase of the output clock signal while undergoing a frequency change operation.

2012018, Jul 26, 2012

Mar 16, 2012

13/422606

Gerald K. Bartley - Rochester MN, US
Russell Dean Hoover - Rochester MN, US
Charles Luther Johnson - Rochester MN, US
Steven Paul VanderWiel - Rosemount MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 23/48

257774, 257777, 257E23011

A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

4939389, Jul 3, 1990

Sep 2, 1988

7/240853

Dennis T. Cox - Rochester MN
David L. Guertin - Rochester MN
Charles L. Johnson - Rochester MN
Bruce G. Rudolph - Rochester MN
Mark E. Turner - Colchester VT
Robert R. Williams - Rochester MN

International Business Machines Corporation - Armonk NY

H03K 19017, H03K 19096

307443

A performance-sensing element (PSE) circuit detects the actual speed of other circuits on the same chip by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.