CHARLES ALLEN CORNELL
Pilots at Sprucewood Cv, Austin, TX

7176720, Feb 13, 2007

Mar 11, 2004

10/798657

Stephen M. Prather - Austin TX, US
Jeffrey F. Waldrip - Austin TX, US
Matthew S. Berzins - Austin TX, US
Charles A. Cornell - Austin TX, US

Cypress Semiconductor Corp. - San Jose CA

H03K 19/0175, H03K 3/45

326 80, 326 81, 330261

Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.

7394293, Jul 1, 2008

Nov 23, 2005

11/286764

Jeffrey Waldrip - Austin TX, US
Stephen M. Prather - Austin TX, US
Matthew Berzins - Austin TX, US
Charles Cornell - Austin TX, US

Cypress Semiconductor Corp. - San Jose CA

H03K 19/0175

326 83, 326 81, 326 68

Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.

6781465, Aug 24, 2004

Dec 13, 2002

10/318543

Matthew S. Berzins - Austin TX
Charles A. Cornell - Austin TX
Stephen M. Prather - Austin TX

Cypress Semiconductor Corp. - San Jose CA

H03F 345

330258, 330 69

Embodiments of the invention describe a method and apparatus for detecting valid differential signals with half the number of differential amplifiers required by conventional methods. By purposely mismatching an otherwise matched differential pair, a self-induced DC offset voltage is created and the additional circuitry required to generate external reference voltages according to conventional methods is eliminated. Embodiments of the invention also have improved noise rejection characteristics and enhanced high-speed capability compared to conventional circuits.

6683818, Jan 27, 2004

Jan 9, 2002

10/042783

Charles A. Cornell - Austin TX
Mathew S. Berzins - Austin TX
Steven P. Larky - Del Mar CA

Cypress Semiconductor Corp. - San Jose CA

G11C 700

365233, 365206, 365207, 365208

A clock may be combined with an asynchronous RAM to create an asynchronous RAM that works within a subset of a full clock period, but allows the address access and other internal RAM functions to occur throughout the clock period. The present invention simplifies the timing analysis of the logic path through the RAM, increases the clock frequency of the resulting logic (compared to a synchronous RAM with narrow timing window), reduces the current requirements (compared to asynchronous RAM), and allows the combinatorial logic to be changed late in the design cycle without the need for a RAM redesign. As more and more logic is synthesized and internal RAM is used to put increasing function on the same die, the structure of the present invention meshes well with synchronous synthesized logic design methodologies, while at the same time recognizes the need to be as stingy as possible with operating current.

7826581, Nov 2, 2010

Oct 5, 2004

10/959259

Stephen M. Prather - Austin TX, US
Matthew S. Berzins - Austin TX, US
Charles A. Cornell - Austin TX, US
Steven P. Larky - Del Mar CA, US
Joseph A. Cetin - San Diego CA, US

Cypress Semiconductor Corporation - San Jose CA

H03D 3/24

375373, 375376

An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

7683697, Mar 23, 2010

May 30, 2008

12/130590

Matthew S. Berzins - Cedar Park TX, US
Charles A. Cornell - Austin TX, US
Andrew P. Hoover - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 3/01

327534

A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

7239178, Jul 3, 2007

Mar 23, 2005

11/090935

Charles A. Cornell - Austin TX, US
Matthew S. Berzins - Cedar Park TX, US
Stephen M. Prather - Austin TX, US

Cypress Semiconductor Corp. - San Jose CA

H03K 19/0175

326 81, 326 68

A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.

8289060, Oct 16, 2012

Jun 22, 2007

11/766880

Samuel J. Tower - Austin TX, US
Matthew S. Berzins - Cedar Park TX, US
Charles A. Cornell - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 3/00

327218, 327215

A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.

7583121, Sep 1, 2009

Aug 30, 2007

11/847424

Matthew S. Berzins - Cedar Park TX, US
Charles A. Cornell - Austin TX, US
Samuel J. Tower - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H03K 3/289

327202, 327218

A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.