CHAN H LEE, MD
Anesthesiologist Assistant in Waunch Prairie, WA

6442674, Aug 27, 2002

Dec 30, 1998

09/223297

Chan Lee - Portland OR
Hitesh Ahuja - Portland OR
Robert F. Krick - Fort Collins CO

Intel Corporation - Santa Clara CA

G06F 9315

712205

A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

5608885, Mar 4, 1997

Mar 1, 1994

8/205022

Ashwani K. Gupta - Beaverton OR
Glenn J. Hinton - Portland OR
Chan W. Lee - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

395380

A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

5845100, Dec 1, 1998

Feb 24, 1997

8/806022

Ashwani Kumar Gupta - Beaverton OR
Glenn J. Hinton - Portland OR
Chan W. Lee - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

395380

A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

6014742, Jan 11, 2000

Dec 31, 1997

9/002166

Robert Franklin Krick - Beaverton OR
Chan Woo Lee - Portland OR
Reynold Viriato D'Sa - Portland OR

Intel Corporation - Santa Clara CA

G06F 938

712236

A trace branch prediction unit includes a trace branch target buffer connected to a trace cache. The trace cache stores traces of micro-ops, with the micro-ops being stored non-sequentially. The trace branch target buffer generally reads a buffer entry corresponding to a particular trace line one clock cycle before the trace line is read to a processor. Using the entry, the trace branch target buffer predicts whether the trace cache should follow the existing trace or leave the trace. If the trace branch target buffer predicts that the trace cache should leave a trace, the trace branch target buffer provides a target address for a new trace. The trace branch target buffer also predicts when a trace is ending and provides a target address for the next trace.

7114057, Sep 26, 2006

Oct 30, 2001

09/984525

Alan B. Kyker - Portland OR, US
Per Hammarlund - Hillsboro OR, US
Chan Lee - Portland OR, US
Robert F. Krick - Fort Collins CO, US
Hitesh Ahuja - Portland OR, US
William Alexander - Hillsboro OR, US
Joseph Rohlman - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 9/318, G06F 9/28

712213, 712211

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

7321963, Jan 22, 2008

Feb 5, 2004

10/773848

Alan B. Kyker - Portland OR, US
Per Hammarlund - Hillsboro OR, US
Chan Lee - Portland OR, US
Robert F. Krick - Fort Collins CO, US
Hitesh Ahuja - Portland OR, US
William Alexander - Hillsboro OR, US
Joseph Rohlman - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 9/318, G06F 9/28

712213, 712211

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

7730281, Jun 1, 2010

Oct 17, 2007

11/974995

Alan B. Kyker - Portland OR, US
Per Hammarlund - Hillsboro OR, US
Chan Lee - Portland OR, US
Robert F. Krick - Fort Collins CO, US
Hitesh Ahuja - Portland OR, US
William Alexander - Hillsboro OR, US
Joseph Rohlman - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 9/318, G06F 9/28

712213, 712211

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.