Carson Donahue Henrion
Engineers in Fort Collins, CO

6812750, Nov 2, 2004

Jun 13, 2003

10/461088

Carson Donahue Henrion - Fort Collins CO
Gary Lewis Taylor - Windsor CO

Hewlett-Packard Development Company, L.P. - Houston TX

H03K 2100

327115, 327117

A clock signal is generated in a remote circuit location by generating a source clock signal, providing at least one digital control signal for determining a ratio between a frequency of the clock signal and the source clock signal, transmitting the source clock signal and the at least one digital control signal to the remote circuit region in which the clock signal is to be used, and generating the clock signal in the remote circuit location based on the source clock signal and the at least one digital control signal.

8031819, Oct 4, 2011

Oct 27, 2006

11/588459

Zhubiao Zhu - Fort Collins CO, US
Carson Donahue Henrion - Fort Collins CO, US
Daniel Alan Berkram - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04L 7/00

375354, 375356, 375355, 375220, 375360, 375376

Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.

7515667, Apr 7, 2009

Nov 9, 2005

11/271398

Carson D. Henrion - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04L 7/00

375354

In one embodiment, a method for reducing synchronizer shadow involves: 1) receiving and deserializing a serialized data flit of known length, under control of a first clock domain; 2) before receiving all of the serialized data flit, beginning to resolve a valid signal for the deserialized data flit in a second clock domain; 3) upon receiving and deserializing all of the serialized data flit, latching the deserialized data flit under control of the first clock domain; and 4) after latching the deserialized data flit, and a predetermined number of clock edges of the second clock domain after beginning to resolve the valid signal, i) resolving the valid signal; and ii) transferring the latched data flit into the second clock domain in response to the valid signal.

7127536, Oct 24, 2006

Sep 30, 2002

10/262006

Gary L. Taylor - Windsor CO, US
Carson D. Henrion - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 3/00, H03K 9/00, H04L 7/00

710 58, 710 5, 710 36, 710 52, 375316, 375354

A source-synchronous data receiver includes a storage device for sequentially storing data received from a data source, a data output device for sequentially outputting the data that is stored in the storage device, and a control for controlling the data output device, so that the data output device makes available particular data previously stored by the data storage device a programmable predetermined number of clock states after data is called for, e. g. , a read command to the data source is initiated.

7019367, Mar 28, 2006

Sep 5, 2003

10/655640

Carson D. Henrion - Fort Collins CO, US
Gary L. Taylor - Windsor CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H01L 23/62

257357, 257173, 257200, 326 31, 326 68, 36518909

An integrated circuit is disclosed herein. One embodiment of the integrated circuit comprises a power supply conductor, a circuit, at least one bypass capacitor, and an electrostatic protection circuit. The circuit may be located on a first piece of silicon, which may be located on a first insulator. The bypass capacitor may be located on a second piece of silicon, which may be located on second insulator. The electrostatic protection circuit may be located on a third piece of silicon, which may be located on a third insulator. The electrostatic protection circuit is connected to the power supply conductor by way of a first line. The bypass capacitor and the circuit are connected to the power supply conductor by way of a second line. The resistance of the second line is greater than the resistance of the first line.

8391432, Mar 5, 2013

Aug 8, 2005

11/199431

Carson D. Henrion - Fort Collins CO, US
Daniel A. Berkram - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04L 7/00

375354, 375355, 375362, 375357

A method of serializing a data stream includes passing a series of data words from a source in a first clock domain to a serializer in a second clock domain and passing valid signals from the source to the serializer indicating when each of the data words is available from the source. The serializer divides each of the data words into a plurality of portions for serial transmission. The method also includes synchronizing the serializer and the source based on the first of the valid signals.