Carl W. Moreland
Residential Contractor at Filmore Rd, Greensboro, NC

License number
North Carolina 39192
Renew Date
Jan 22, 1998
Category
General Contractor
Type
Residential
Address
Address
4314 Filmore Rd, Greensboro, NC 27409
Phone
(910) 665-1592

Professional information

Carl Moreland Photo 1

Intermediate Frequency (If) Sampling Clock-To-Clock Auto-Ranging Analog-To-Digital Converter (Adc) And Method

US Patent:
5861831, Jan 19, 1999
Filed:
Dec 23, 1996
Appl. No.:
8/772358
Inventors:
Franklin M. Murden - Greensboro NC
Carl W. Moreland - Greensboro NC
Harvey J. Ray - Salem NC
Michael R. Elliott - Greensboro NC
Marvin J. Young - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03M 162
US Classification:
341139
Abstract:
A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.


Carl Moreland Photo 2

Analog To Digital Converter Having A Magnitude Amplifier With An Improved Differential Input Amplifier

US Patent:
5554943, Sep 10, 1996
Filed:
Dec 1, 1994
Appl. No.:
8/347704
Inventors:
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc.
International Classification:
H03K 524, H03M 172
US Classification:
327 65
Abstract:
An improved magnitude amplifier (magamp) is provided for a serial-type A/D converter. The magamp includes an improved differential input amplifier circuit to which offset circuitry is connected. These elements may be implemented in a single integrated circuit chip or as separate discrete circuits in hardware. The differential input amplifier circuit includes two pairs of differential input transistors, a comparator, and current switching control transistors. The comparator provides outputs that drive the current switching control transistors. The current switching control transistors are connected below the input transistors and not above the input transistors to reduce the parasitic capacitive loading at the outputs of the differential input amplifier circuit and increase the speed of the magamp. The offset circuitry provides the appropriate signals for aligning the output signals for output to the next stage magamp.


Carl Moreland Photo 3

N-Bit Analog-To-Digital Converter With N-1 Magnitude Amplifiers And N Comparators

US Patent:
5684419, Nov 4, 1997
Filed:
Dec 1, 1994
Appl. No.:
8/347909
Inventors:
Frank Murden - Greensboro NC
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03M 112, H03M 146
US Classification:
327104
Abstract:
A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V. sub. OL and V. sub. OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V. sub.


Carl Moreland Photo 4

Gain-Compensating Differential Reference Circuit

US Patent:
5673047, Sep 30, 1997
Filed:
Jun 6, 1995
Appl. No.:
8/465885
Inventors:
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03M 118
US Classification:
341139
Abstract:
A gain compensating differential reference circuit that is used to match the gain of an input differential amplifier, and track and hold circuit at the input of an analog-to-digital converter. The gain compensating differential reference circuit includes a single-to-differential converter to convert a V. sub. REF signal into a V. sub. REF+ and a V. sub. REF- signals whose difference equals the full-scale range of the differential analog input to the A/D converter, a gain matching differential amplifier to process to the differential output of the single-to-differential converter, and a gain matching track and hold circuit to process the output of the differential amplifier. The output of the gain matching track and hold circuit has the same gain and full-scale range as the analog signals processed by the input circuitry of the A/D converter along the analog path.


Carl Moreland Photo 5

Selectable Logic Output Stage

US Patent:
5534794, Jul 9, 1996
Filed:
Dec 1, 1994
Appl. No.:
8/347710
Inventors:
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 190175
US Classification:
326 63
Abstract:
A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.


Carl Moreland Photo 6

Digitally Controlled Programmable Attenuator

US Patent:
5757220, May 26, 1998
Filed:
Dec 23, 1996
Appl. No.:
8/772359
Inventors:
Franklin M. Murden - Greensboro NC
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03G 300
US Classification:
327308
Abstract:
A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0. 2. degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized. The buffers can be implemented with complementary bipolar or BiCMOS processes.


Carl Moreland Photo 7

Input Or Output Selectable Circuit Pin

US Patent:
5539338, Jul 23, 1996
Filed:
Dec 1, 1994
Appl. No.:
8/348052
Inventors:
Carl W. Moreland - Greensboro NC
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 519
US Classification:
327 19
Abstract:
A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.