CAMERON DOUGLAS PATTERSON
Pilots at Shelor Ln, Blacksburg, VA
License number
Virginia A4106335
Issued Date
Apr 2016
Expiration Date
Apr 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
1907 Shelor Ln, Blacksburg, VA 24060
Professional information
Hardware-Facilitated Secure Software Execution Environment
US Patent:
8473754, Jun 25, 2013
Filed:
Feb 20, 2007
Appl. No.:
11/707951
Inventors:
Mark T. Jones - Blacksburg VA, US
Peter M. Athanas - Newport VA, US
Cameron D. Patterson - Blacksburg VA, US
Joshua N. Edmison - Ellicott City MD, US
Anthony Mahar - Merrimack NH, US
Benjamin J. Muzal - Fairfax VA, US
Barry L. Polakowski - Roanoke VA, US
Jonathan P. Graf - Blacksburg VA, US
Peter M. Athanas - Newport VA, US
Cameron D. Patterson - Blacksburg VA, US
Joshua N. Edmison - Ellicott City MD, US
Anthony Mahar - Merrimack NH, US
Benjamin J. Muzal - Fairfax VA, US
Barry L. Polakowski - Roanoke VA, US
Jonathan P. Graf - Blacksburg VA, US
Assignee:
Virginia Tech Intellectual Properties, Inc. - Blacksburg VA
Macaulay-Brown, Inc. - Dayton OH
Macaulay-Brown, Inc. - Dayton OH
International Classification:
G06F 11/30, H04L 9/32, H04L 9/00, H04K 1/00
US Classification:
713190, 713171, 380 28, 380277
Abstract:
A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.
Method And System For Generating A Bitstream View Of A Design
US Patent:
7343578, Mar 11, 2008
Filed:
Aug 12, 2004
Appl. No.:
10/917064
Inventors:
Cameron D. Patterson - Blacksburg VA, US
Prasanna Sundararajan - Mountain View CA, US
Brandon J. Blodget - Santa Clara CA, US
Scott P. McMillan - Santa Clara CA, US
Prasanna Sundararajan - Mountain View CA, US
Brandon J. Blodget - Santa Clara CA, US
Scott P. McMillan - Santa Clara CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 16, 716 17, 716 18
Abstract:
A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e. g. , one or more of a PLD design's essential configuration bits) and a logical circuit description (e. g. , one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.
Method And System For Identifying Essential Configuration Bits
US Patent:
7406673, Jul 29, 2008
Filed:
Aug 12, 2004
Appl. No.:
10/917033
Inventors:
Cameron D. Patterson - Blacksburg VA, US
Prasanna Sundararajan - Mountain View CA, US
Brandon J. Blodget - Santa Clara CA, US
Scott P. McMillan - Santa Clara CA, US
Prasanna Sundararajan - Mountain View CA, US
Brandon J. Blodget - Santa Clara CA, US
Scott P. McMillan - Santa Clara CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50, G06F 9/00, G06F 15/177, G06F 1/24
US Classification:
716 16, 716 18, 713 2, 713100
Abstract:
A method and system are disclosed. The method and system provide the ability to identify a configuration bit as an essential configuration bit. The identifying that is performed uses a configuration bit definition.
Method And Apparatus For Dynamically Connecting Modules In A Programmable Device
US Patent:
7669168, Feb 23, 2010
Filed:
Sep 27, 2006
Appl. No.:
11/527963
Inventors:
Cameron D. Patterson - Blacksburg VA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 19, 716 2, 716 6, 716 17, 716 18
Abstract:
Method and apparatus for dynamically connecting modules within a programmable device is described. In an example, a programmable device is programmed with modular circuits. A bitstream is obtained from a database. The bitstream includes a first portion associated with a module and a second portion associated with an interface to the module. The bitstream is then modified with configuration data to connect the interface to one or more of the modular circuits. The programmable device is then configured using the modified bitstream.
Wires On Demand: Run-Time Communication Synthesis For Reconfigurable Computing
US Patent:
7902866, Mar 8, 2011
Filed:
Aug 27, 2008
Appl. No.:
12/199465
Inventors:
Cameron Patterson - Blacksburg VA, US
Peter Athanas - Newport VA, US
John K. Bowen - Alexandria VA, US
Timothy G. Dunham - Roanoke VA, US
Justin D. Rice - Coral Springs FL, US
Matthew T. Shelburne - Christiansburg VA, US
Jorge A. Suris Pletri - Blacksburg VA, US
Jonathan Graf - Blacksburg VA, US
Peter Athanas - Newport VA, US
John K. Bowen - Alexandria VA, US
Timothy G. Dunham - Roanoke VA, US
Justin D. Rice - Coral Springs FL, US
Matthew T. Shelburne - Christiansburg VA, US
Jorge A. Suris Pletri - Blacksburg VA, US
Jonathan Graf - Blacksburg VA, US
Assignee:
Virginia Tech Intellectual Properties, Inc. - Blacksburg VA
International Classification:
H03K 19/177
US Classification:
326 41, 326 38
Abstract:
A method, and system, for reconfiguring an FPGA which has a static region and a dynamic region is provided. The method includes the steps of: (a) providing a dynamic module library having information of predetermined modules; (b) receiving a reconfiguration request external to the FPGA; (c) computing reconfiguration of the FPGA at a predetermined location using predetermined module information from the dynamic module library and the reconfiguration request, and generating reconfigurable partial bitstreams; and (d) sending partial bitstreams from the predetermined location to the FPGA to perform the reconfiguration.