DR. BRUCE E ULRICH, D.C.
Chiropractic at Baseline St, Beaverton, OR

License number
Oregon 1528
Category
Chiropractic
Type
Chiropractor
Address
Address
527 SE Baseline St SUITE D, Beaverton, OR 97123
Phone
(503) 330-0123

Personal information

See more information about BRUCE E ULRICH at radaris.com
Name
Address
Phone
Bruce Ulrich, age 71
3629 SE 64Th Ave, Portland, OR 97206
(503) 206-8057
Bruce Ulrich
14095 SW Barlow Ct, Beaverton, OR 97008
(503) 407-9349
Bruce Ulrich, age 72
13625 SW Berthold St, Beaverton, OR 97005
(503) 643-6195
Bruce F Ulrich, age 71
3629 64Th Ave, Portland, OR 97206
(503) 777-0419
(503) 206-8057
Bruce D Ulrich, age 73
14095 Barlow Rd, Beaverton, OR 97008
(503) 644-3543

Organization information

See more information about BRUCE E ULRICH at bizstanding.com

Bruce E Ulrich DC

328 W Main St Ste C, Hillsboro, OR 97123

Phone:
(503) 640-8929 (Phone)
Owner:
Bruce Ulrich (Owner)
Categories:
Chiropractors D.C.

Professional information

Bruce Ulrich Photo 1

Method Of Making Self-Aligned Shallow Trench Isolation

US Patent:
6627510, Sep 30, 2003
Filed:
Mar 29, 2002
Appl. No.:
10/112014
Inventors:
David R. Evans - Beaverton OR
Sheng Teng Hsu - Camas WA
Bruce D. Ulrich - Beaverton OR
Douglas J. Tweet - Camas WA
Lisa H. Stecker - Vancouver WA
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
H01L 21762
US Classification:
438401, 438975
Abstract:
A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer.


Bruce Ulrich Photo 2

Mfmos Capacitors With High Dielectric Constant Materials

US Patent:
6716645, Apr 6, 2004
Filed:
Dec 12, 2002
Appl. No.:
10/319314
Inventors:
Tingkai Li - Vancouver WA
Sheng Teng Hsu - Camas WA
Hong Ying - San Jose CA
Bruce D. Ulrich - Beaverton OR
Yanjun Ma - Vancouver WA
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
H01L 2100
US Classification:
438 3
Abstract:
A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO , HfO , Y O , or La O , or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.


Bruce Ulrich Photo 3

Multiple Exposure Masking System For Forming Multi-Level Resist Profiles

US Patent:
5753417, May 19, 1998
Filed:
Jun 10, 1996
Appl. No.:
8/665013
Inventors:
Bruce Dale Ulrich - Beaverton OR
Assignee:
Sharp Microelectronics Technology, Inc. - Camas WA
Sharp Kabushiki Kaisha - Osaka
International Classification:
G03F 900
US Classification:
430312
Abstract:
A method is provided for forming multi-level profiles from a photoresist mask. The method includes exposing selected areas of a photoresist layer to two or more different patterns of light at different light dosage levels. For example, one pattern will be exposed to a relatively low dose of light, or to light for a short duration, and a second pattern will be exposed to a relatively high dose of light, or for a greater duration. The plurality of different exposures at different dosage levels occur prior to developing the photoresist. When the photoresist layer is developed, the pattern exposed to a lower dose of light will be etched substantially more slowly than the areas of the photoresist exposed to higher dose of light. By controlling the development process to completely remove the resist in the areas exposed to a high dose of light and only partially remove the resist in the areas exposed to a lower dose of light, a multi-level photoresist profile is formed. Such a multi-level profile can then be used in subsequent semiconductor processing, for example, the formation of interconnects and vias.


Bruce Ulrich Photo 4

Selective Etching Processes Of Sio, Ti And Inothin Films For Feram Device Applications

US Patent:
7364665, Apr 29, 2008
Filed:
Oct 21, 2004
Appl. No.:
10/970885
Inventors:
Tingkai Li - Vancouver WA, US
Bruce D. Ulrich - Beaverton OR, US
David R. Evans - Beaverton OR, US
Sheng Teng Hsu - Camas WA, US
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
B44C 1/22, C03C 15/00, C03C 25/68, C23F 1/00
US Classification:
216 72, 216 67
Abstract:
A method of selectively etching a three-layer structure consisting of SiO, InO, and titanium, includes etching the SiO, stopping at the titanium layer, using CFin a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the InOlayer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tin a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.


Bruce Ulrich Photo 5

Method For Forming An Iridium Oxide (Irox) Nanowire Neural Sensor Array

US Patent:
7905013, Mar 15, 2011
Filed:
Jun 4, 2007
Appl. No.:
11/809959
Inventors:
Fengyan Zhang - Camas WA, US
Bruce D. Ulrich - Beaverton OR, US
Wei Gao - Vancouver WA, US
Sheng Teng Hsu - Camas WA, US
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
H01K 3/10
US Classification:
29852, 29831, 29832, 29853, 29854
Abstract:
An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO, ZnO, TiO, doped ITO, doped SnO, doped ZnO, doped TiO, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0. 5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.


Bruce Ulrich Photo 6

Multi-Level Reticle System And Method For Forming Multi-Level Resist Profiles

US Patent:
5936707, Aug 10, 1999
Filed:
Jan 16, 1998
Appl. No.:
9/008362
Inventors:
Tue Nguyen - Vancouver WA
Bruce Dale Ulrich - Beaverton OR
David Russell Evans - Beaverton OR
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
Sharp Kabushiki Kaisha - Osaka
International Classification:
G03B 2700, G03B 2728, G03B 2704
US Classification:
355 18
Abstract:
A method is providing for making a multi-level reticle which transmits a plurality of incident light intensities, which in turn, are used to form a plurality of thicknesses in a photoresist profile. A partially transmitting film, used as one of the layers of the reticle, is able to provide an intermediate intensity light. The intermediate intensity light has an intensity approximately midway between the intensity of the unattenuated light passing through the reticle substrate layer, and the totally attenuated light blocked by an opaque layer of the reticle. The exposed photoresist receives light at two intensities to form a via hole in the resist in response to the higher intensity light, and a connecting line to the via at an intermediate level of the photoresist in response to the intermediate light intensity. A method for forming the multi-level resist profile from the multi-level reticle is provided as well as a multi-level reticle apparatus.


Bruce Ulrich Photo 7

Error Diffusion-Derived Sub-Resolutional Grayscale Reticle

US Patent:
7897302, Mar 1, 2011
Filed:
Oct 7, 2008
Appl. No.:
12/247130
Inventors:
Bruce D. Ulrich - Beaverton OR, US
Yoshi Ono - Camas WA, US
Wei Gao - Vancouver WA, US
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
G03F 1/00, G06F 17/50
US Classification:
430 5, 716 19
Abstract:
A method is provided for forming an error diffusion-derived sub-resolutional grayscale reticle. The method forms at least one partial-light transmissive layer overlying a transparent substrate. At least one unit cell in formed in the transmissive layer. The unit cell is formed by selecting the number of reduced-transmission pixels in the unit cell, and forming a sub-pattern of reduced-transmission pixels in the unit cell. The unit cell is sub-resolutional at a first wavelength.


Bruce Ulrich Photo 8

Semi-Transparent Film Grayscale Mask

US Patent:
2009014, Jun 4, 2009
Filed:
Dec 4, 2007
Appl. No.:
11/950196
Inventors:
Wei Gao - Vancouver WA, US
Bruce D. Ulrich - Beaverton OR, US
Yoshi Ono - Camas WA, US
International Classification:
G03F 1/00
US Classification:
430 5
Abstract:
A grayscale mask made from semi-transparent film layers is provided, along with an associated fabrication method. The method provides a transparent substrate, such as quartz, with a surface. A first layer of a semi-transparent film having a surface with a first surface area, is formed overlying the substrate surface. At least a second layer of the semi-transparent film having a surface with a second surface area greater than the first surface area, is formed overlying the first layer. A first vertical region is formed having a light first attenuation parameter through the combination of substrate, first layer, and second layer. A second vertical region is formed having a light second attenuation parameter through the combination of the first layer and substrate, and a third vertical region is formed having a light third attenuation parameter through the substrate.


Bruce Ulrich Photo 9

Selective Etching Processes For Inothin Films In Feram Device Applications

US Patent:
7053001, May 30, 2006
Filed:
Sep 30, 2003
Appl. No.:
10/676983
Inventors:
Tingkai Li - Vancouver WA, US
Sheng Teng Hsu - Camas WA, US
Bruce Dale Ulrich - Beaverton OR, US
Assignee:
Sharp Laboratories of America, Inc. - Camas WA
International Classification:
H01I 21/302
US Classification:
438710, 240706, 240720
Abstract:
A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.


Bruce Ulrich Photo 10

Grayscale Reticle For Precise Control Of Photoresist Exposure

US Patent:
7439187, Oct 21, 2008
Filed:
Oct 27, 2006
Appl. No.:
11/588891
Inventors:
Yoshi Ono - Camas WA, US
Bruce D. Ulrich - Beaverton OR, US
Pooran Chandra Joshi - Vancouver WA, US
Assignee:
Sharp Laboratories of America - Camas WA
International Classification:
H01L 21/00, H01L 21/302
US Classification:
438717, 438 34, 438 48, 438942, 257E21023
Abstract:
A method of fabricating a grayscale reticule includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticule; and using the reticule to pattern a microlens array.