BRIAN R JOHNSON, S.P.
Speech Language Pathology at 120 Ave, Bellevue, WA
License number
Washington LL00003248
Category
Speech Language Pathology
Type
Speech-Language Pathologist
Address
Address
626 120Th Ave NE SUITE B201, Bellevue, WA 98005
Phone
(425) 556-6330
(425) 556-6325 (Fax)
(425) 502-3898
(425) 502-4233 (Fax)
(425) 556-6325 (Fax)
(425) 502-3898
(425) 502-4233 (Fax)
Personal information
See more information about BRIAN R JOHNSON at radaris.comName
Address
Phone
4852 Dr Eldridge Dr, Washougal, WA 98671
4901 Lake Washington Blvd S, Seattle, WA 98118
4823 80Th St E, Tacoma, WA 98443
4821 Ne 71St St, Seattle, WA 98115
4770 Beachcomber Dr, Blaine, WA 98230
Professional information
Project Manager At Philips Healthcare
Position:
Project Manager at Philips Healthcare
Location:
Greater Seattle Area
Industry:
Computer Software
Work:
Philips Healthcare
- Bothell, WA since Jul 2012
-
Project Manager
Avaya
- Bellevue, WA Oct 2010 - Jun 2012
-
Project Management in Quality Assurance
Avaya
- Bellevue, WA Jul 2001 - Sep 2010
-
Tier IV/Current Engineering
Avaya
- Redmond, WA Jun 2000 - Jul 2001
-
Third Party Developer Support
Concur Technologies
- Redmond, WA 1997 - Jun 2000
-
Sales Engineer
Education:
Eastern Washington University
Computer Information Systems, Computer Science Eastern Washington University
Management Information Systems, Business Administration
Computer Information Systems, Computer Science Eastern Washington University
Management Information Systems, Business Administration
Skills:
Program Management, Network Traffic Analysis, Lean Software Development, Six Sigma, Software Development, Software Design, Software Project Management, Sales Engineering, Development & delivery of training, International Development, International Business Development, Customer Service, Troubleshooting, Telecommunications, Agile Application Development, CORBA, Java, C ++, ISDN, Visual Basic
Portfolio Manager At Appropriate Balance Financial Services, Inc.
Position:
Portfolio Manager at Appropriate Balance Financial Services, Inc.
Location:
Greater Seattle Area
Industry:
Investment Management
Work:
Appropriate Balance Financial Services, Inc.
- Bellevue, WA since Jun 2012
-
Portfolio Manager
Skills:
Portfolio Management, Investments, Equities, ETFs, Investment Strategies, Asset Managment, Asset Allocation, Private Equity, Angel Investing, Fixed Income, Risk Management, Technical Analysis, Social Media, Stock Market, Investment Management
Brian Johnson - Issaquah, WA
Work:
CRAY, INC
Manager, Signal Integrity Engineering CRAY, INC. - Seattle, WA
Technical Lead, Circuits ALTERA CORPORATION - San Jose, CA
Lead Circuits engineer TERADYNE, INC - Boston, MA
Co-op Intern in High-Speed Digital Design Group
Manager, Signal Integrity Engineering CRAY, INC. - Seattle, WA
Technical Lead, Circuits ALTERA CORPORATION - San Jose, CA
Lead Circuits engineer TERADYNE, INC - Boston, MA
Co-op Intern in High-Speed Digital Design Group
Education:
CORNELL UNIVERSITY - Ithaca, NY
Bachelor of Science in Electrical Engineering
Bachelor of Science in Electrical Engineering
Brian R Johnson, Bellevue WA - SP
Specialties:
Speech-Language Pathology
Address:
626 120Th Ave NE SUITE B201, Bellevue 98005
(425) 556-6330 (Phone), (425) 556-6325 (Fax)
(425) 556-6330 (Phone), (425) 556-6325 (Fax)
Languages:
English
Techniques For Providing Increased Flexibility To Input/Output Banks With Respect To Supply Voltages
US Patent:
7196542, Mar 27, 2007
Filed:
Oct 28, 2004
Appl. No.:
10/977332
Inventors:
Andy Lee - San Jose CA, US
Toan Nguyen - San Francisco CA, US
Stephanie Tran - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Bellevue WA, US
Toan Nguyen - San Francisco CA, US
Stephanie Tran - San Jose CA, US
Cameron McClintock - Mountain View CA, US
Brian Johnson - Bellevue WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 41, 326 82
Abstract:
Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.
High-Performance Memory Interface Circuit Architecture
US Patent:
8305121, Nov 6, 2012
Filed:
Jun 24, 2011
Appl. No.:
13/168499
Inventors:
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
327161, 327158, 327159
Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
High-Performance Memory Interface Circuit Architecture
US Patent:
7535275, May 19, 2009
Filed:
Apr 24, 2007
Appl. No.:
11/789598
Inventors:
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
327161, 327158, 327159
Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
High-Performance Memory Interface Circuit Architecture
US Patent:
7969215, Jun 28, 2011
Filed:
May 18, 2009
Appl. No.:
12/467681
Inventors:
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
327161, 327158, 327159
Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
High-Performance Memory Interface Circuit Architecture
US Patent:
7227395, Jun 5, 2007
Filed:
Feb 9, 2005
Appl. No.:
11/055125
Inventors:
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/00
US Classification:
327161, 327158, 327159
Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
High Performance Memory Interface Circuit Architecture
US Patent:
8593195, Nov 26, 2013
Filed:
Sep 13, 2012
Appl. No.:
13/614526
Inventors:
Joseph Huang - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Chiakang Sung - Milpitas CA, US
Philip Pan - Fremont CA, US
Yan Chong - San Jose CA, US
Andy L. Lee - San Jose CA, US
Brian D. Johnson - Issaquah WA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03H 11/16
US Classification:
327231, 327234
Abstract:
A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
Speech Language Pathology licenses in Washington
JENNIFER A KELLOGG-SMITH, Speech Language Pathology, 710 NW Juniper St SUITE 108, Bellevue, WA 98027