Brian Paul Johnson
Optometry in Boise, ID

6522172, Feb 18, 2003

Mar 20, 2001

09/812757

Brent Keeth - Boise ID
Brian Johnson - Boise ID

Micron Technology, Inc. - Boise ID

H03K 1903

326 95, 326 98, 326 93, 365203, 36518905

A circuit having a data input pin for receiving a data signal, a clock input for receiving a clock signal and having a low setup time and a zero hold time is comprised of an input stage for periodically connecting a sampling device to the data input pin in response to the clock signal. An evaluation stage, responsive to the clock signal, evaluates the charge collected by the device at a time the device is disconnected from the data input pin. The evaluation stage produces a signal representative of the sampled charge. An output stage, responsive to the clock signal and the produced signal, outputs a data signal representative of the sampled data signal. The circuit may have a single data path and a single charge accumulating device such that an output signal representative of the sampled data signal is available on either the rising or the falling edge of the clock signal. Alternatively, multiple data paths may be provided as well as multiple charge accumulating devices so that data signals representative of the sampled data may be output on both the rising and the falling edge of the clock signal. The circuit can be operated as either a latch or a register.

6697297, Feb 24, 2004

Aug 29, 2002

10/230673

Brent Keeth - Boise ID
Brian Johnson - Boise ID

Micron Technology, Inc. - Boise ID

G11C 800

365233, 365194, 36518904

A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

6605970, Aug 12, 2003

May 10, 2000

09/569047

Brent Keeth - Boise ID
Brian Johnson - Boise ID

Micron Technology, Inc. - Boise ID

G06F 106

327159, 327158, 327233, 365233

Disclosed is a method and apparatus for converting an unstable receiver enable signal RXEN, which is based on a master clock which undergoes timing adjustments, to a stable receiver enable signal RXEN′ which is based on an externally applied clock signal. An externally applied clock signal at a frequency fc is divided by a factor N to produce N uniformly phase spaced clock signals. A clocking edge of a master clock signal which generates the receiver enable signal RXEN is associated with one of the N clocking signals which has a pulse which substantially envelopes the edge of the master clock signal which generates the RXEN signal. A new receiver enable signal RXEN′ is generated by the associated new clock signal. The receiver enable signal RXEN is therefore converted from a signal which has adjusted timing to RXEN′ which has no timing adjustment.

6934199, Aug 23, 2005

Dec 11, 2002

10/317429

Christopher S. Johnson - Meridian ID, US
Brian Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C007/00

365194, 36518905, 365233

A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

6842398, Jan 11, 2005

Nov 7, 2003

10/703275

Brian Johnson - Boise ID, US
Brent Keeth - Boise ID, US
Jeffrey W. Janzen - Meridian ID, US
Troy A. Manning - Meridian ID, US
Chris G. Martin - Boise ID, US

Micron Technology, Inc. - Boise ID

G11C 800

365233, 365194, 36523001, 327269, 327141, 327155

A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

6333893, Dec 25, 2001

Aug 21, 2000

9/642090

Brent Keeth - Boise ID
Brian Johnson - Boise ID

Micron Technology, Inc. - Boise ID

G11C 800

365233

A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.

7013252, Mar 14, 2006

Sep 2, 1999

09/388766

Brian Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G06F 17/50, G06F 13/10, G06F 9/45

703 14, 703 20, 716 5

An initial condition (IC) behavior module is described for use in a hardware definition language simulation system which operates in two phases. In the first phase, the IC module sets an initial logic condition onto a user-selected node which is to be monitored. The IC module will release the initial condition and then test the node value to determine if the simulation system is able to resolve the node. Alternatively, the IC module may release the node if a user-defined IC time period passes. In the second phase, the IC module monitors the node and reports an error message if the simulated node value becomes unacceptable.

7160795, Jan 9, 2007

Nov 12, 2002

10/293789

Shubneesh Batra - Boise ID, US
Michael D. Chaine - Boise ID, US
Brent Keeth - Boise ID, US
Salman Akram - Boise ID, US
Troy A. Manning - Meridian ID, US
Brian Johnson - Boise ID, US
Chris G. Martin - Boise ID, US
Todd A. Merritt - Boise ID, US
Eric J. Smith - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/44

438612, 438618, 438622

A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

7913035, Mar 22, 2011

Apr 12, 2010

12/758598

Brian Johnson - Boise ID, US

Micron Technology, Inc. - Boise ID

G06F 12/00, G06F 3/00

711105, 710 52, 710 53, 711E12001

A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.