DR. BRIAN LEE, M.D.
Medical Practice at Longwood Ave, Boston, MA

8289759, Oct 16, 2012

Apr 21, 2011

13/091372

Xiaobin Wang - Chanhassen MN, US
Yong Lu - Edina CA, US
Haiwen Xi - San Jose CA, US
Yuankai Zheng - Fremont CA, US
Yiran Chen - Eden Prairie MN, US
Harry Hongyue Liu - Maple Grove MN, US
Dimitar V. Dimitrov - Edina MN, US
Wei Tian - Bloomington MN, US
Brian S. Lee - Boston MA, US

Seagate Technology LLC - Scotts Valley CA

G11C 11/00

365158, 36518522, 36518519

A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.

2012008, Apr 5, 2012

Sep 30, 2010

12/894405

Peter Nicholas Manos - Eden Prairie MN, US
Young Pil Kim - Eden Prairie MN, US
Hyung-Kyu Lee - Edina MN, US
Yongchul Ahn - San Jose CA, US
Jinyoung Kim - Edina MN, US
Antoine Khoueir - Apple Valley MN, US
Brian Lee - Boston MA, US
Dadi Setiadi - Edina MN, US

SEAGATE TECHNOLOGY LLC - Scotts Valley CA

H01L 27/08, H01L 21/02

257208, 438382, 257329, 257E21004, 257E27046

A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

2014001, Jan 16, 2014

Jul 10, 2013

13/938628

Brian Lee - Boston MA, US
Jamshed Dubash - Shrewsbury MA, US
Mrinmoy Chakraborty - Bangalore IN, US

G06Q 10/08, G06Q 50/28

455 412

Wireless tracking systems and devices to detect the status of cargo containers, such as aircraft cargo. The system has a transmitter device, a router, and intelligent software. The transmitter device has automatic on-off capability during use, without the need for human intervention. The transmitter device has a basic “listening state” and the router has a basic “beacon broadcast state.” Only when the transmitter device is within range of the router's beacon does the device transmit data via RF signal to the router.

8197953, Jun 12, 2012

Apr 11, 2011

13/083693

Haiwen Xi - Prior Lake MN, US
Antoine Khoueir - Apple Valley MN, US
Brian Lee - Boston MA, US
Pat Ryan - St. Paul MN, US
Michael Tang - Bloomington MN, US
Insik Jin - Eagan MN, US
Paul E. Anderson - Eden Prairie MN, US

Seagate Technology LLC - Scotts Valley CA

G11B 5/39, H01F 10/08, H01L 43/08, H01L 43/12

4288111, 4288115, 36032411, 36032412, 365158, 257421, 32420721

A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer.

7936622, May 3, 2011

Jul 13, 2009

12/502194

Hai Li - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Dadi Setiadi - Edina MN, US
Harry Hongyue Liu - Maple Grove MN, US
Brian Lee - Boston MA, US

Seagate Technology LLC - Scotts Valley CA

G11C 29/00

365200, 365180, 365 491, 365130, 365201

Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

8050072, Nov 1, 2011

Jun 24, 2009

12/490493

Hai Li - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Yuan Yan - Edina MN, US
Brian Lee - Boston MA, US
Ran Wang - Irvine CA, US

Seagate Technology LLC - Scotts Valley CA

G11C 5/06

365 63, 365206, 365207, 365163

A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.