Inventors:
Peter Nicholas Manos - Eden Prairie MN, US
Young Pil Kim - Eden Prairie MN, US
Hyung-Kyu Lee - Edina MN, US
Yongchul Ahn - San Jose CA, US
Jinyoung Kim - Edina MN, US
Antoine Khoueir - Apple Valley MN, US
Brian Lee - Boston MA, US
Dadi Setiadi - Edina MN, US
Assignee:
SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:
H01L 27/08, H01L 21/02
US Classification:
257208, 438382, 257329, 257E21004, 257E27046
Abstract:
A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.