Brian Lee Miller
Veterinary at Basil Ln, Fort Collins, CO

6567966, May 20, 2003

Feb 14, 2001

09/783434

Brian C. Miller - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G06F 1750

716 10, 716 8

Systems and methods are presented for decreasing the effect of Miller capacitance on adjacent interconnects in an integrated circuit. The systems and methods include interweaving interconnects with signals traveling in one direction with interconnects with signals traveling in the opposite direction. The systems include a system for fabricating integrated circuits with interweaved interconnects and an integrated circuit with interweaved interconnects.

6703869, Mar 9, 2004

Jun 5, 2002

10/164169

Darrin C. Miller - Fort Collins CO
Brian C Miller - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

H03K 1920

326104, 326 21, 326 22, 326101

A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

6539507, Mar 25, 2003

Nov 10, 1999

09/437813

Christopher M Juenemann - Aurora CO
Bradley J Goertzen - Ft. Collins CO
Rory L Fisher - Fort Collins CO
Randy L Fiscus - Ft. Collins CO
Brian C Miller - Fort Collins CO
Peter J Meier - Fort Collins CO
Joel Buck-Gengler - Longmont CO
Kenneth S Bower - Ft. Collins CO
Michael R Diehl - Fort Collins CO
Dale R Beucler - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G01R 3128

714726

An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

6429683, Aug 6, 2002

Aug 16, 2000

09/640259

Darrin C. Miller - Fort Collins CO
Brian C Miller - Ft Collins CO

Agilent Technologies, Inc. - Palo Alto CA

H03K 190185

326 80, 326 81, 326 68, 363 60

An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.

5831991, Nov 3, 1998

Dec 13, 1996

8/763371

Brian C. Miller - Fort Collins CO
Alan S. Krech - Fort Collins CO

Hewlett-Packard Co. - Palo Alto CA

G01R 3128

371 221

Apparatus for electrically verifying a functional unit contained within an integrated circuit comprises a functional unit, a state machine, a number of integrated circuit input pins, and means for alternately providing the functional unit with control data derived from the state machine, and control data derived from the number of integrated circuit input pins. The means for providing control data from alternating sources comprises a multiplexor which receives a first set of inputs from the state machine, and a second set of inputs from a test control block. The test control block monitors various of the integrated circuit input pins for a designated instruction, receives control data via the input pins, and controls the operation of the multiplexor. The test control block comprises a number of test registers which can be configured to receive two or more states of control data. An additional multiplexor, internal to the test control block, may then be used to sequentially provide successive states of "test" control data to the functional unit.

5796288, Aug 18, 1998

Oct 15, 1996

8/730170

Alan S. Krech - Fort Collins CO
Brian C. Miller - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

H03K 17693

327407

A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

8543967, Sep 24, 2013

Feb 24, 2012

13/405059

Jason T. Gentry - Windsor CO, US
Brian C. Miller - Fort Collins CO, US
William S. Burton - Fort Collins CO, US
M. Jason Welch - Fort Collins CO, US
Richard A. Krzyzkowski - Fort Collins CO, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

G06F 17/50

716136, 716106, 716109, 716110, 716111

A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.

6124869, Sep 26, 2000

May 20, 1998

9/082172

Brian C. Miller - Fort Collins CO
Peter J. Meier - Fort Collins CO

Agilent Technologies - Palo Alto CA

G06F 1300

345523

A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.