BRIAN E SMITH, M.D.
Anesthesiologist Assistant at Mowry Ave, Fremont, CA
License number
California G76268
Category
Osteopathic Medicine
Type
Anesthesiology
Address
Address
2
2000 Mowry Ave, Fremont, CA 94538
Po Box V, Mountain View, CA 94040
Po Box V, Mountain View, CA 94040
Phone
(510) 797-1111
(650) 691-0611
(650) 691-0611
Organization information
See more information about BRIAN E SMITH at bizstanding.comBrian E. Smith, M.D., A Medical Corporation
1503 Grant Rd, Mountain View, CA 94040
Status:
Inactive
Industry:
Health/Allied Services
Doing business as:
Brian E Smith MD
Phone:
(650) 988-7444 (Phone)
Categories:
Anesthesiology Physicians
Professional information
Brian Smith - Fremont, CA
Work:
St.Rose Hospital
Registered Respiratory Therapist/RCP2
Registered Respiratory Therapist/RCP2
Education:
Ohlone College - Fremont, CA
A.S in Respiratory Therapy
A.S in Respiratory Therapy
Skills:
Team Leadership
Dr. Brian E Smith, Fremont CA - MD (Doctor of Medicine)
Specialties:
Anesthesiology
Address:
2000 Mowry Ave, Fremont 94538
(510) 797-1111 (Phone)
Northern California Anesthesia Associates
1503 Grant Rd SUITE 150, Mountain View 94040
(510) 797-1111 (Phone)
Northern California Anesthesia Associates
1503 Grant Rd SUITE 150, Mountain View 94040
Certifications:
Anesthesiology, 1998
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
2000 Mowry Ave, Fremont 94538
Northern California Anesthesia Associates
1503 Grant Rd SUITE 150, Mountain View 94040
Washington Hospital
2000 Mowry Ave, Fremont 94538
Northern California Anesthesia Associates
1503 Grant Rd SUITE 150, Mountain View 94040
Washington Hospital
2000 Mowry Ave, Fremont 94538
Education:
Medical School
University Of Washington School Of Medicine
Graduated: 1991
Providence Hospital
Graduated: 1992
Stanford University
Graduated: 1995
Graduated: 1996
University Of Washington School Of Medicine
Graduated: 1991
Providence Hospital
Graduated: 1992
Stanford University
Graduated: 1995
Graduated: 1996
Integrated Circuit Device Core Power Down Independent Of Peripheral Device Operation
US Patent:
8327173, Dec 4, 2012
Filed:
Dec 17, 2007
Appl. No.:
12/002711
Inventors:
Neil Hendin - Mountain View CA, US
Zahid Najam - San Jose CA, US
Stephane Le Provost - San Jose CA, US
Brian Smith - Mountain View CA, US
Zahid Najam - San Jose CA, US
Stephane Le Provost - San Jose CA, US
Brian Smith - Mountain View CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 1/00
US Classification:
713323
Abstract:
In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.
Use Methods For Power Optimization Using An Integrated Circuit Having Power Domains And Partitions
US Patent:
2009020, Aug 13, 2009
Filed:
Feb 11, 2008
Appl. No.:
12/029442
Inventors:
Brian Smith - Mountain View CA, US
Parthasarathy Sriram - Los Altos CA, US
Stephane Le Provost - San Jose CA, US
Parthasarathy Sriram - Los Altos CA, US
Stephane Le Provost - San Jose CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 1/32, G06F 1/00
US Classification:
713323, 713300
Abstract:
In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality.
Powered Ring To Maintain Io Independent Of The Core Of An Integrated Circuit Device
US Patent:
2009025, Oct 15, 2009
Filed:
Apr 10, 2008
Appl. No.:
12/101028
Inventors:
Brian Smith - Mountain View CA, US
Ewa Kubalska - Los Gatos CA, US
Ewa Kubalska - Los Gatos CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
H03K 3/02
US Classification:
327198
Abstract:
In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.
System And Method For Power Optimization
US Patent:
2011021, Sep 1, 2011
Filed:
May 25, 2010
Appl. No.:
12/787361
Inventors:
John George Mathieson - San Jose CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
International Classification:
G06F 1/32, G06F 15/76
US Classification:
713324, 712 16, 712E09001
Abstract:
A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.
System And Method For Using Inputs As Wake Signals
US Patent:
2009020, Aug 13, 2009
Filed:
Feb 11, 2008
Appl. No.:
12/029346
Inventors:
Neil Hendin - Mountain View CA, US
Ewa Kubalska - Los Gatos CA, US
Zahid Najam - San Jose CA, US
Stephane Le Provost - San Jose CA, US
Brian Smith - Mountain View CA, US
Ewa Kubalska - Los Gatos CA, US
Zahid Najam - San Jose CA, US
Stephane Le Provost - San Jose CA, US
Brian Smith - Mountain View CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event.
Power Management Techniques For Usb Interfaces
US Patent:
2014004, Feb 13, 2014
Filed:
Aug 9, 2012
Appl. No.:
13/571299
Inventors:
Eric L. Masson - Fremont CA, US
Matthew R. Longnecker - Sunnyvale CA, US
Hemalkumar Chandrakant Doshi - Sunnyvale CA, US
Brian Smith - Mountain View CA, US
Matthew R. Longnecker - Sunnyvale CA, US
Hemalkumar Chandrakant Doshi - Sunnyvale CA, US
Brian Smith - Mountain View CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 1/32, G06F 1/00, G06F 1/26
US Classification:
713324, 713320, 713300
Abstract:
Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state.
System And Method For Power Optimization
US Patent:
2012033, Dec 27, 2012
Filed:
Sep 5, 2012
Appl. No.:
13/604390
Inventors:
John George Mathieson - San Jose CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
International Classification:
G06F 9/318
US Classification:
712220, 712E09035
Abstract:
A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.
System And Method For Power Optimization
US Patent:
2012033, Dec 27, 2012
Filed:
Sep 5, 2012
Appl. No.:
13/604496
Inventors:
John George Mathieson - San Jose CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
Phil Carmack - Santa Clara CA, US
Brian Smith - Mountain View CA, US
International Classification:
G06F 1/32, G06F 12/08, G06F 9/30
US Classification:
713320, 712220, 711122, 712E09016, 711E12024
Abstract:
A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.