Brian David Parker
Architects in Salt Lake City, UT
License number
Utah 6294273-0301
Issued Date
Aug 14, 2006
Expiration Date
May 31, 2018
Category
Architect
Type
Architect
Address
Address
Salt Lake City, UT
Professional information
See more information about Brian David Parker at trustoria.com
Associate Principal At Mhtn Architects
Associate Principal At Mhtn Architects
Position:
Associate Principal at MHTN Architects
Location:
Greater Salt Lake City Area
Industry:
Design
Work:
MHTN Architects
since 2001
-
Associate Principal
Education:
San Diego State University-California State University 2009 - 2010
Certificate in Educational Facility Design and Planning, K-12 Facility Planning and Design University of Utah 1995 - 1999
Master in Architecture, Architecture
Certificate in Educational Facility Design and Planning, K-12 Facility Planning and Design University of Utah 1995 - 1999
Master in Architecture, Architecture
Languages:
Dutch
System For Memory Instantiation And Management
System For Memory Instantiation And Management
US Patent:
2011023, Sep 22, 2011
Filed:
Jun 29, 2010
Appl. No.:
12/826419
Inventors:
Aaron Gelter - West Jordan UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Assignee:
HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED - Northridge CA
International Classification:
G06F 12/02
US Classification:
711171, 711E12007
Abstract:
A system for memory instantiation in a programmable logic device (PLD) includes a computing device having a processor and memory coupled with the PLD. The processor is configured to receive memory parameters including at least a data width and a data depth. The processor is also configured to determine a number and sizes of block random access memory (BRAM) primitives required for data storage based on the memory parameters and based on one or more sizes of BRAM primitives available on the programmable logic device. In one example, the processor minimizes a size of the total number of BRAMs required for instantiation on the PLD. The processor is also configured to instantiate the determined number and corresponding sizes of the BRAM primitives in logic for configuration of the programmable logic device to include a device memory within the available BRAM primitives thereof corresponding to the determined number and sizes of the BRAM primitives.
Dynamic Instruction And Data Updating Architecture
Dynamic Instruction And Data Updating Architecture
US Patent:
8074053, Dec 6, 2011
Filed:
Nov 15, 2006
Appl. No.:
11/599967
Inventors:
James D. Pennock - Salt Lake City UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Assignee:
Harman International Industries, Incorporated - Northridge CA
International Classification:
G06F 9/00
US Classification:
712 25, 712225
Abstract:
A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the processor to seamlessly continue operation during a live performance.
Stream Identifier Hash Table
Stream Identifier Hash Table
US Patent:
2011023, Sep 22, 2011
Filed:
Feb 9, 2011
Appl. No.:
13/023989
Inventors:
Aaron Gelter - West Jordan UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Jeffrey L. Hutchings - Lehi UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Jeffrey L. Hutchings - Lehi UT, US
Assignee:
HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED - Northridge CA
International Classification:
G06F 15/16
US Classification:
709231
Abstract:
A system may route media stream samples in time-stamped packets to a media interface. The system may determine a hash value from a stream identifier that identifies a source media stream corresponding to the media stream samples. The hash value may be determined based on a combination of a first portion of the stream identifier and a second portion of the stream identifier. The system may determine whether the stream identifier identifies a subscribed media stream by looking up the hash value in a hash table. The system may route the media stream samples to a media interface if source media stream is a subscribed media stream.
Memory Management Unit
Memory Management Unit
US Patent:
8443098, May 14, 2013
Filed:
Feb 9, 2011
Appl. No.:
13/024008
Inventors:
Aaron Gelter - West Jordan UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Richard A. Kreifeldt - Sandy UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Richard A. Kreifeldt - Sandy UT, US
Assignee:
Harman International Industries, Incorporated - Stamford CT
International Classification:
G06F 15/16
US Classification:
709231, 709246
Abstract:
A memory management unit (MMU) may buffer media stream samples of one or more media streams, such as audio and/or video streams, in a buffer. The MMU may determine how much time a media stream sample is to be buffered by comparing a value of a real-time clock with a timestamp associated with the media stream sample. The MMU may determine a target output block in the buffer for the media stream sample based on the period of a media clock and on the amount of buffer time that the media stream sample is to be buffered. The target output block is determined relative to an output block identified by a read address. The MMU may store the media stream sample in the target output block. The MMU may increase or decrease the read address at a rate determined by the media clock.
External Memory Interface Engine
External Memory Interface Engine
US Patent:
2008001, Jan 17, 2008
Filed:
Jun 29, 2007
Appl. No.:
11/771764
Inventors:
James D. Pennock - Salt Lake City UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
International Classification:
G06F 12/00
US Classification:
711148, 711E12006
Abstract:
A configurable device interface enhances the ability of a processor to communicate with other devices. The configurable device interface provides programmers with an efficient mechanism for communicating with a wide variety of external memories, each of which may have their own unique interface requirements. As a result, the configurable device interface permits a data processor to operate without hard coded dedicated state machines, and without waiting for an external memory to complete an instruction before the data processor may perform its next instruction.
Interleaved Hardware Multithreading Processor Architecture
Interleaved Hardware Multithreading Processor Architecture
US Patent:
8429384, Apr 23, 2013
Filed:
Nov 15, 2006
Appl. No.:
11/599732
Inventors:
James D. Pennock - Salt Lake City UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Assignee:
Harman International Industries, Incorporated - Northridge CA
International Classification:
G06F 9/38, G06F 15/76
US Classification:
712 35, 712219, 712221
Abstract:
An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction awaits the result of a prior instruction. The architecture coordinates the processing of data for multiple instructions through a multiple stage data pipeline. As a result, the architecture not only supports simultaneous execution of multiple programs, but also permits each program to execute without delays caused by inter-relationships between instructions within the program.
Serial Communication Input Output Interface Engine
Serial Communication Input Output Interface Engine
US Patent:
2008001, Jan 17, 2008
Filed:
Jun 29, 2007
Appl. No.:
11/771743
Inventors:
James D. Pennock - Salt Lake City UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
Ronald Baker - Sandy UT, US
Brian R. Parker - West Valley City UT, US
Christopher Belcher - Lehi UT, US
International Classification:
G06F 3/00
US Classification:
710 52
Abstract:
A configurable device interface enhances the ability of a processor to communicate with other devices. A configurable serial interface promotes efficient data transmission and reception. The configurable serial interface includes a source of transmit data that the configurable serial interface may access even while data reception is simultaneously completing.
Media Clock Recovery
Media Clock Recovery
US Patent:
8428045, Apr 23, 2013
Filed:
Sep 2, 2010
Appl. No.:
12/874836
Inventors:
Aaron Gelter - West Jordan UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Brian Parker - West Valley City UT, US
Robert Boatright - Sandy UT, US
Assignee:
Harman International Industries, Incorporated - Stamford CT
International Classification:
H04W 64/00
US Classification:
370350, 370503, 370507, 370512, 370516, 375371, 375376
Abstract:
A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter.