BRIAN DAVID LARSON
Pilots at Diamond Ct, Saint Paul, MN

6504841, Jan 7, 2003

Oct 26, 1999

09/426466

Brian Ralph Larson - Eagan MN
Charles Kryzak - Mendota Heights MN

Lockheed Martin Corporation - Bethesda MD

H04L 1250

370386, 3408255

Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred “layered network” of U. S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U. S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.

4498177, Feb 5, 1985

Aug 30, 1982

6/412487

Brian R. Larson - Eagan MN

Sperry Corporation - New York NY

H03K 1332

371 52

An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln. sub. 2 (N/3)+1 bits width at level ln. sub. 2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2. sup. X+1. gtoreq. N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M. ltoreq.

8538526, Sep 17, 2013

Dec 16, 2010

12/970613

Jeffrey E. Stahmann - Ramsey MN, US
Michael A. Querimit - Fridley MN, US
Donald L. Hopper - Maple Grove MN, US
Brian Ralph Larson - Shoreview MN, US
Paul F. Emerson - St. Louis Park MN, US
Daniel O'Brien - St. Paul MN, US

Cardiac Pacemakers, Inc. - St. Paul MN

A61N 1/365

607 20, 607 19

A rate-adaptive pacemaker and a method for its operation in which the response factor for a minute ventilation sensor or other type of exertion level sensor is automatically set during a parameter adjustment mode that utilizes an activity level measurement to determine when the patient is at a target activity level with which is associated an appropriate target pacing rate. In a preferred embodiment, the target activity level corresponds to casual walking (e. g. , 2 mph at a 4% grade) with a target pacing rate selected as appropriate for that level of activity in the individual patient.

6215786, Apr 10, 2001

Apr 6, 1998

9/055396

Brian Ralph Larson - Eagan MN
Steven Allen Murphy - Apple Valley MN

Lockheed Martin Corporation - Bethesda MD

H04L 1250

370386

Multi-stage switching networks may be constructed and expanded from small to very large networks that are contained within a compact physical volume. This is accomplished by replication of a pre-selected network module containing switches by a rotating, folding and squaring process that substantially reduces the length of connections between switches. This geometry allows very large networks by inductively combining smaller networks into larger networks. In networks constructed with this geometry, the length of the longest connections between switches is proportional to the square root of the number of ports provided by the network.

6212179, Apr 3, 2001

Feb 27, 1998

9/032534

Steven Allen Murphy - Apple Valley MN
Donald Bruce Bennett - Apple Valley MN
Brian Ralph Larson - Eagan MN

Lockheed Martin Corporation - Bethesda MD

H04L 1250

370370

An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.