BRETT WILLIAM BUSCH
Pilots at Rockrose Way, Boise, ID

2006026, Nov 23, 2006

May 18, 2005

11/131555

Brett Busch - Boise ID, US
David Hwang - Boise ID, US
F. Gealy - Kuna ID, US

H01L 21/4763, H01L 21/8242

438239000, 438618000, 438622000, 438396000

The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

8580690, Nov 12, 2013

Apr 6, 2011

13/080676

Brett Busch - Boise ID, US
Gowri Damarla - Boise ID, US
Anurag Jindal - Boise ID, US
Chia-Yen Ho - New Taipei, TW
Thy Tran - Boise ID, US

Nanya Technology Corp. - Kueishan, Tao-Yuan Hsien

H01L 21/306

438692, 257E2123

A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

2005018, Aug 25, 2005

Feb 20, 2004

10/783843

Brett Busch - Boise ID, US
Luan Tran - Meridian ID, US
Ardavan Niroomand - Boise ID, US
Fred Fishburn - Boise ID, US
Yoshiki Hishiro - Boise ID, US
Ulrich Boettiger - Boise ID, US
Richard Holscher - Boise ID, US

H01L021/8234, H01L021/8242, H01L021/8244, H01L021/302, H01L021/461

438736000, 438239000

A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

7538036, May 26, 2009

Aug 31, 2005

11/216759

Brett W. Busch - Boise ID, US
Luan C. Tran - Meridian ID, US
Ardavan Niroomand - Boise ID, US
Fred D. Fishburn - Boise ID, US
Yoshiki Hishiro - Boise ID, US
Ulrich C. Boettiger - Boise ID, US
Richard D. Holscher - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/3205

438695, 438703, 438743, 438744, 438761, 438942

A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

8030168, Oct 4, 2011

Apr 6, 2009

12/419014

Brett W. Busch - Boise ID, US
David K. Hwang - Boise ID, US
F. Daniel Gealy - Kuna ID, US

Micron Technology, Inc. - Boise ID

H01L 21/8242

438396, 438244, 438253, 438387, 438618, 977773, 257E21586, 257E21658

The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

7445990, Nov 4, 2008

Feb 24, 2006

11/362063

Brett W. Busch - Boise ID, US
Fred D. Fishburn - Boise ID, US
James Rominger - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/8242

438253, 438396, 257E27087

A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material. Then, the sacrificial retaining structure is removed from the substrate, and then capacitor dielectric material and conductive second capacitor electrode material are formed over the outer sidewall surfaces of the first capacitor electrode material formed within the first and second sets of capacitor openings.

8058126, Nov 15, 2011

Feb 4, 2009

12/365519

Brett Busch - Boise ID, US
Kevin R. Shea - Boise ID, US
Thomas A. Figura - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/8242

438253, 438396, 257296, 257E21648, 257E21646

Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.

2014005, Feb 27, 2014

Aug 21, 2012

13/590791

Zhimin Song - Boise ID, US
Che-Chi Lee - Banciao, TW
Brett Busch - Boise ID, US

MICRON TECHNOLOGY, INC. - Boise ID

H01L 27/108, H01L 21/8242

257532, 438381, 257E27084, 257E21647

Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.

7618874, Nov 17, 2009

May 2, 2008

12/114124

Kevin Shea - Boise ID, US
Brett Busch - Boise ID, US
Farrell Good - Meridian ID, US
Irina Vasilyeva - Boise ID, US
Vishwanath Bhat - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/20, H01L 21/108

438396, 438250, 438253, 438381, 257 68, 257 71, 257296

A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.