Inventors:
Brent Kelley - Round Rock TX, US
William Brantley - Austin TX, US
International Classification:
G06F013/00
Abstract:
A processor surrogate () is adapted for use in a processing node (S) of a multiprocessor data processing system () having a plurality of processing nodes (P, S) coupled together and to a plurality of input/output devices () using corresponding communication links. The processor surrogate () includes a first port () comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link () for coupling (P) of the plurality of processing nodes (), a second port () comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link () for coupling to one () of the plurality of input/output devices (), and an interconnection circuit () coupled between the first port () and the second port ().