BRENT ARNOLD MYERS
Pilots at Neville Cir, Melbourne, FL

6405022, Jun 11, 2002

May 17, 2000

09/572417

Richard D. Roberts - Palm Bay FL
Brent A. Myers - Palm Bay FL
James C. Richards - Fairfax VA
Eric C. Black - Mountain View CA

Intersil Americas Inc. - Irvine CA

H04B 140

455 76, 455 86

A radio frequency transceiver includes a radio frequency processor having a modulator/demodulator phase locked loop circuit for generating a second intermediate frequency signal. A heterodyne frequency translation loop circuit receives the second intermediate frequency signal and outputs a first intermediate frequency signal. A transmit mixer receives the first intermediate frequency signal and outputs a transmit radio frequency signal fo. A synthesizer circuit is operatively connected to the transmit mixer and the heterodyne frequency translation loop circuit for generating an oscillation signal to the transmit mixer and the heterodyne frequency translation loop circuit. The oscillation signal is divided down by factor N before passing into the heterodyne frequency translation loop circuit.

6346856, Feb 12, 2002

May 16, 2000

09/571822

Brent A. Myers - Palm Bay FL
Ramkishore Ganti - Waltham MA

Intersil Americas Inc. - Irvine CA

H03F 345

330252, 330258

A transconductor block including a Czarnul tuning network, transconductance resistors, an input voltage follower amplifier, a common mode circuit, PMOS transistors coupled in cascode configuration, an input current source, and high gain amplifiers that drive NMOS transistors at the output. The input voltage follower amplifier receives a differential input signal including a common mode voltage and applies the differential input signal to the Czarnul tuning network. The Czarnul tuning network includes series resistors and is coupled in parallel with the transconductance resistors. The common mode circuit receives the differential input signal and a reference common mode voltage and provides a bias voltage and a common mode feedback voltage. The common mode circuit asserts the common mode feedback voltage to the output PMOS transistors to establish a DC output current and to minimize drift of the common mode voltage of the transconductance block. Also, the bias voltage is level shifted from the common mode signal.

2013006, Mar 14, 2013

Nov 9, 2012

13/672912

BRENT ARNOLD MYERS - PALM BAY FL, US
JAMES GREGORY FOX - INDIALANTIC FL, US

CHAOLOGIX, INC. - Gainesville FL

H01L 25/00, H03K 19/094

326 44, 326102

Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

5666083, Sep 9, 1997

Nov 17, 1995

8/560289

Brent A. Myers - Palm Bay FL
Scott G. Bardsley - Palm Bay FL

Harris Corporation - Melbourne FL

H03K 500, H03F 345

327553

A circuit and method for adjusting a cutoff frequency of an active filter, such as a gm-C filter, which has a common mode feedback circuit for providing a bias signal may include plural common base stages having first inputs connected in parallel to a stage of the active filter and second inputs connected in parallel to an output from the common mode feedback circuit, and a capacitor connected to an output from each of the common base stages. The common base stages and their connected capacitors are selectively isolated from the filter output to adjust the cutoff frequency of the filter. The deselected common base stages are also isolated from the common mode feedback circuit and bias generator inputs.

5119321, Jun 2, 1992

May 14, 1990

7/523020

Willie T. Burton - Palm Bay FL
Brent A. Myers - Palm Bay FL
William W. Wiles - W. Melbourne FL

Harris Corporation - Melbourne FL

H03F 126

364574

Impulse noise suppression upstream of digital processing circuitry contains a sample and hold mechanism which samples the input signal and stores a plurality of sequential sample values respectively representative of the amplitude of the input signal at successive sample times. The contents of the sample and hold mechanism are compared with an input signal sample to determine whether or not the there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude of the input signal. In another embodiment the input signal is coupled to a cascaded arrangement of sample and hold circuits which sample and store a plurality of sequential sample values. The time differentials between successive sampling times are such there is little likelihood of occurrences of impulse noise spikes during any two successive sample intervals. The contents of the last sample and hold circuit of the cascaded plurality are compared with the contents of each of selected other sample and hold circuits of the cascaded chain.

5572161, Nov 5, 1996

Jun 30, 1995

8/497045

Brent A. Myers - Palm Bay FL

Harris Corporation - Melbourne FL

H03K 17687, G05F 326

327538

A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i. e. ,. mu. C. sub. ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.

5659269, Aug 19, 1997

Mar 13, 1995

8/402381

Brent A. Myers - Palm Bay FL

Harris Corporation - Melbourne FL

H03L 7093

331 17

A loop filter for a phase locked loop (PLL) circuit may include two operational amplifiers and switched-capacitors connecting the inverted input and output of the operational amplifiers, the switched-capacitors replacing resistors found in conventional loop filters for PLL circuits. The loop filter may be in a monolithic integrated circuit, and the PLL circuit may operate with a response time heretofore available only with individual (non-IC) components. Phase error due to amplifier offset may be reduced with offset nulling techniques.

6233293, May 15, 2001

Jun 17, 1999

9/334998

Brent A. Myers - Palm Bay FL
Paul J. Godfrey - Melbourne FL

Intersil Corporation - Palm Bay FL

H04L 2706

375344

Spurious energy suppression for a data communication system is achieved without using a large order noise suppression filter, by means of a post-mixer tracking filter that contains a current-controlled MOSFET-implemented resistance for a transconductance-capacitance filter and an associated transconductance tuning stage. The MOSFET-implemented resistance is controlled by the same control current that establishes the output frequency. As a result, the cut-off frequency of the tracking filter is linearly proportional to the carrier and independent of absolute processing parameters and temperature.

4893088, Jan 9, 1990

Nov 16, 1988

7/271656

Brent A. Myers - Palm Bay FL
William W. Wiles - West Melbourne FL

Harris Corporation - Melbourne FL

G11C 2702, H03F 108

328127

A transimpedance processor includes a feedback circuit for generating a voltage as a function of the input background level and precharging the capacitor of the input integrator to a negative of the generated voltage in a precharge cycle.