BHARAT R PATEL, RPH
Pharmacy at Mcabee Rd, San Jose, CA
License number
California 44319
Category
Pharmacy
Type
Pharmacist
Address
Address
6264 Mcabee Rd, San Jose, CA 95120
Phone
(408) 931-2657
Personal information
See more information about BHARAT R PATEL at radaris.comName
Address
Phone
4760 S Broadway, Los Angeles, CA 90037
493 Eddy St #4, San Francisco, CA 94109
493 Eddy St, San Francisco, CA 94109
4952 Roja Dr, Oceanside, CA 92057
454 Hawthorne St, Glendale, CA 91204
Organization information
See more information about BHARAT R PATEL at bizstanding.comBharat R Patel RPH
6264 Mcabee Rd, San Jose, CA 95120
Industry:
Nonclassifiable Establishments
Professional information
Bharat Patel - San Jose, CA
Work:
Intel
Manager of a cross-site design team Intel - Santa Clara, CA
Tech Lead and Project Execution Lead Intel - Santa Clara, CA
Microprocessor Unit Team Lead Intel - Santa Clara, CA
ASIC Design Engineer Intel - Santa Clara, CA
Software Development Engineer Intel - Santa Clara, CA
(RV) Design Automation Engineer
Manager of a cross-site design team Intel - Santa Clara, CA
Tech Lead and Project Execution Lead Intel - Santa Clara, CA
Microprocessor Unit Team Lead Intel - Santa Clara, CA
ASIC Design Engineer Intel - Santa Clara, CA
Software Development Engineer Intel - Santa Clara, CA
(RV) Design Automation Engineer
Education:
Penn State University
Master of Science in Electrical Engg University of Bombay - Mumbai, Maharashtra
Bachelor of Engineering in Electronics Engg
Master of Science in Electrical Engg University of Bombay - Mumbai, Maharashtra
Bachelor of Engineering in Electronics Engg
Integrated Circuit Structure Having Compensating Means For Self-Inductance Effects
US Patent:
4737830, Apr 12, 1988
Filed:
Jan 8, 1986
Appl. No.:
6/817227
Inventors:
Bharat D. Patel - San Jose CA
Stephen Y. Tam - San Francisco CA
Pravin R. Shah - Sunnyvale CA
Stephen Y. Tam - San Francisco CA
Pravin R. Shah - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2978
US Classification:
357 236
Abstract:
An improved integrated circuit structure is disclosed which comprises a Vcc bus and a Vss bus having capacitance means coupled between the busses and distributed along the length of the busses to reduce the voltage spikes induced during switching. In a preferred embodiment, the capacitance means comprise one or more capacitors formed beneath one of the busses. Construction of MOS capacitors beneath one or more of the busses is disclosed.
Power Supply Acoustic Noise Mitigation
US Patent:
2013033, Dec 12, 2013
Filed:
Nov 30, 2012
Appl. No.:
13/691678
Inventors:
David R. COX - Los Gatos CA, US
Bharat K. PATEL - San Jose CA, US
Nicholas W. RUHTER - San Francisco CA, US
Xiaoyang ZHANG - Fremont CA, US
Steve X. ZHOU - San Jose CA, US
Bharat K. PATEL - San Jose CA, US
Nicholas W. RUHTER - San Francisco CA, US
Xiaoyang ZHANG - Fremont CA, US
Steve X. ZHOU - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 1/26
US Classification:
713340, 713300
Abstract:
A method and system for reducing acoustic power supply noise, specifically acoustic noise related to power supply switching frequencies in a computing device, is disclosed. In one embodiment, a controller can monitor power consumed by the computing device, and an operational state of the computing device can be determined. If the computing device is in a first operational state and the power consumed is greater than a threshold amount, then the power supply can be operated at a first switching frequency or mode of operation, thereby avoiding switching frequencies that can produce acoustic noise.
Integrated Circuit Chip With Repeater Flops And Methods For Automated Design Of Same
US Patent:
8607178, Dec 10, 2013
Filed:
Apr 30, 2012
Appl. No.:
13/460747
Inventors:
Stuart A. Taylor - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716114, 716100, 716110, 716119, 716122, 716126
Abstract:
An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.
Bleeder Circuitry For Increasing Leakage Current During Hiccup Modes Of Power Adapters
US Patent:
2013032, Dec 12, 2013
Filed:
Oct 9, 2012
Appl. No.:
13/648131
Inventors:
Bharat K. Patel - San Jose CA, US
Abby Cherian - Sunnyvale CA, US
Abby Cherian - Sunnyvale CA, US
Assignee:
APPLE INC. - Cupertino CA
International Classification:
H02J 1/00
US Classification:
307130
Abstract:
The disclosed embodiments provide a system that facilitates operation of a power adapter in hiccup mode. The system includes a bleeding mechanism that reduces a hiccup time of the hiccup mode by increasing a leakage current of the power adapter. The system also includes an activation mechanism that activates the bleeding mechanism upon detecting a voltage drop associated with the hiccup mode.
Integrated Circuit Chip With Repeater Flops And Method For Automated Design Of Same
US Patent:
2008006, Mar 13, 2008
Filed:
Aug 17, 2007
Appl. No.:
11/840660
Inventors:
Stuart Taylor - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
Victor Ma - Fremont CA, US
Bharat Patel - San Jose CA, US
International Classification:
G06F 17/50, H03K 19/0175
US Classification:
716010000, 326062000
Abstract:
An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.
Power Supply Input Routing
US Patent:
2013031, Nov 28, 2013
Filed:
May 7, 2013
Appl. No.:
13/889220
Inventors:
Kathleen A. BERGERON - Los Gatos CA, US
John Douglas FIELD - Los Gatos CA, US
Edward H. FRANK - Atherton CA, US
Michelle R. GOLDBERG - Sunnyvale CA, US
Harsha LAKSHMANAN - Fremont CA, US
Manisha P. PANDYA - Sunnyvale CA, US
Bharat K. PATEL - San Jose CA, US
Deborah Claire SHARRAH - Santa Clara CA, US
Steve Xing-Fu ZHOU - San Jose CA, US
John Douglas FIELD - Los Gatos CA, US
Edward H. FRANK - Atherton CA, US
Michelle R. GOLDBERG - Sunnyvale CA, US
Harsha LAKSHMANAN - Fremont CA, US
Manisha P. PANDYA - Sunnyvale CA, US
Bharat K. PATEL - San Jose CA, US
Deborah Claire SHARRAH - Santa Clara CA, US
Steve Xing-Fu ZHOU - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H05K 1/02, H02M 1/12, H02M 7/00
US Classification:
363 44, 363147, 174251
Abstract:
One embodiment of a power supply input routing apparatus can include a multilayer printed circuit board configured to accept only an alternating current (AC) line voltage, return and ground signals. The AC power jumper board can advantageously route AC power from one section of the power supply to another without burdening the power supply design with extra layer requirements or negatively increasing power supply area. Embodiments including an electronic device having a power supply as above are also disclosed.