MR. BARRY N. DAVIS, DO
Medical Practice at Sunnyside Rd, Happy Valley, OR

6460108, Oct 1, 2002

Mar 31, 1999

09/282386

Jeff J. McCoskey - Phoenix AZ
Richard P. Mackey - Phoenix AZ
Barry R. Davis - Portland OR

Intel Corporation - Santa Clara CA

G06F 1300

710310, 710 57, 710305, 710306, 710307

A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.

6298407, Oct 2, 2001

Mar 4, 1998

9/034624

Barry R. Davis - Portland OR
Nick G. Eskandari - Chandler AZ

Intel Corporation - Santa Clara CA

G06F 1300

710129

Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.

7007126, Feb 28, 2006

Feb 13, 1998

09/023494

Byron R. Gillespie - Scottsdale AZ, US
Barry R. Davis - Portland OR, US
William Futral - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 13/38

710306, 370402, 711202

An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (IO®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the IO protocol without interrupting the host processor which normally resides on the primary PCI bus.