AUGUSTUS KINZEL UHT
Engineers in Valley Falls, RI
License number
Pennsylvania PE033579E
Category
Engineers
Type
Professional Engineer
Address
Address
2
Valley Falls, RI 02864
Pennsylvania
Pennsylvania
Professional information
System For Extracting Low Level Concurrency From Serial Instruction Streams
US Patent:
5201057, Apr 6, 1993
Filed:
Feb 5, 1990
Appl. No.:
7/474247
Inventors:
Augustus K. Uht - Cumberland RI
International Classification:
G06F 704
US Classification:
395800
Abstract:
An architecture for a central processing unit (cpu) provides for the extraction of low-level concurrency from sequential instruction streams. The cpu includes an instruction queue, a plurality of processing elements, a sink storage matrix for temporary storage of data elements, and relational matrixes storing dependencies between instructions in the queue. An execution matrix stores the dynamic execution state of the instructions in the queue. An executable independence calculator determines which instructions are eligible for execution and the location of source data elements. New techniques are disclosed for determining data independence of instructions, for branch prediction without state restoration or backtracking, and for the decoupling of instruction execution from memory updating.
Not-Taken Path Instruction For Selectively Generating A Forwarded Result From A Previous Instruction Based On Branch Outcome
US Patent:
8601245, Dec 3, 2013
Filed:
Jul 15, 2011
Appl. No.:
13/183662
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 9/30
US Classification:
712226, 712239
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.
System And Method Of Digital System Performance Enhancement
US Patent:
7555084, Jun 30, 2009
Filed:
Aug 11, 2005
Appl. No.:
11/202656
Inventors:
Augustus K. Uht - Cumberland RI, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
H04L 7/00
US Classification:
375354, 375376, 375371, 327145
Abstract:
The present invention performs a digital computation with a lower than worst-case-required clock period (i. e. , a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i. e. , a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i. e. , a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e. g. , speed), albeit with more hardware.
System And Method Of Digital System Performance Enhancement
US Patent:
6985547, Jan 10, 2006
Filed:
Nov 26, 2003
Appl. No.:
10/723592
Inventors:
Augustus K. Uht - Cumberland RI, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
H04L 7/00
US Classification:
375354, 375376, 375371, 327145
Abstract:
The present invention performs a digital computation with a lower than worst-case-required clock period (i. e. , a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i. e. , a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i. e. , a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e. g. , speed), albeit with more hardware.
Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates
US Patent:
7210025, Apr 24, 2007
Filed:
Apr 19, 2001
Appl. No.:
09/838678
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.
Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates
US Patent:
7380108, May 27, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515220
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
Board of Govenors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.
Automatic And Transparent Hardware Conversion Of Traditional Control Flow To Predicates
US Patent:
7409534, Aug 5, 2008
Filed:
Aug 31, 2006
Appl. No.:
11/515374
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 15/00
US Classification:
712226
Abstract:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.
System And Method For Cache Replacement
US Patent:
7721048, May 18, 2010
Filed:
Mar 15, 2007
Appl. No.:
11/686851
Inventors:
Resit Sendag - Wakefield RI, US
Ayse Yilmazer - Marlborough MA, US
Augustus K. Uht - Cumberland RI, US
Ayse Yilmazer - Marlborough MA, US
Augustus K. Uht - Cumberland RI, US
Assignee:
Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 12/00, G06F 13/00, G06F 13/28, G06F 15/00, G06F 7/38, G06F 9/00, G06F 9/44
US Classification:
711133, 711136, 711118, 712233, 712239, 712237
Abstract:
A computer processing system is disclosed that includes a cache that includes cache blocks of data. The system includes a marking sub-system, an ordering sub-system, and a replacement sub-system. The marking sub-system identifies and marks cache blocks that were provided to the cache via a wrong path with marking data. The ordering sub-system provides an order in which the cache blocks of data will be replaced in the cache, and the ordering sub-system is responsive to the marking data. The replacement sub-system replaces cache blocks in the cache in accordance with the ordering sub-system as required.
Concurrent Execution Of Instructions In A Processing System
US Patent:
7991980, Aug 2, 2011
Filed:
Oct 20, 2008
Appl. No.:
12/254684
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F 9/30
US Classification:
712217
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.
Resource Flow Computing Device
US Patent:
6976150, Dec 13, 2005
Filed:
Apr 6, 2001
Appl. No.:
09/828600
Inventors:
Augustus K. Uht - Cumberland RI, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
David Morano - Malden MA, US
David Kaeli - Medway MA, US
Assignee:
The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI
International Classification:
G06F015/173
US Classification:
712 18, 712 26, 712201, 712215
Abstract:
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.