ARNOLD STEVEN TRAN
Pilots at Ml Pond Ln, Burlington, VT

5930832, Jul 27, 1999

Jun 7, 1996

8/660560

Jay Gerald Heaslip - Williston VT
Robert Dov Herzl - South Burlington VT
Arnold Steven Tran - South Burlington VT

International Business Machines Corporation - Armonk NY

G06F 1210

711207

A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e. g. , PASS 2 or later), thus avoiding a necessity for complex recovery provisions.

7962695, Jun 14, 2011

Dec 4, 2007

11/949935

Marc R. Faucher - South Burlington VT, US
Hillery C. Hunter - Somers NY, US
William R. Reohr - Ridgefield CT, US
Peter A. Sandon - Essex Junction VT, US
Vijayalakshmi Srinivasan - New York NY, US
Arnold S. Tran - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 12/00, G06F 13/00, G06F 13/28

711136, 711128, 711E12043

A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.

2009019, Jul 30, 2009

Apr 15, 2008

12/103290

Philip G. Emma - Danbury CT, US
Hillery C. Hunter - Somers NY, US
Vijayalakshmi Srinivasan - New York NY, US
Arnold S. Tran - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711106, 711E12001

A design structure for an embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.

2013000, Jan 3, 2013

Jun 28, 2011

13/171027

Jason F. Cantin - Round Rock TX, US
Jack R. Smith - South Burlington VT, US
Arnold S. Tran - South Burlington VT, US
Kenichi Tsuchiya - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 9/38

712240, 712E09045

Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.

2009019, Jul 30, 2009

Jan 25, 2008

12/019818

Philip G. Emma - Danbury CT, US
Hillery C. Hunter - Somers NY, US
Vijayalakshmi Srinivasan - New York NY, US
Arnold S. Tran - Burlington VT, US

G06F 12/00

711106, 711E12001

An embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.

8024513, Sep 20, 2011

Dec 4, 2007

11/949904

Philip G. Emma - Danbury CT, US
Erik L. Hedberg - Essex Jct. VT, US
Hillery C. Hunter - Somers NY, US
Peter A. Sandon - Essex Jct. VT, US
Vijayalakshmi Srinivasan - New York NY, US
Arnold S. Tran - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 12/00

711106, 711105, 711153, 711172, 711E12017

A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

7882302, Feb 1, 2011

Dec 4, 2007

11/949859

Marc R. Faucher - South Burlington VT, US
Peter A. Sandon - Essex Junction VT, US
Arnold S. Tran - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 13/00

711106, 711128

A method for implementing prioritized refresh of a multiple way, set associative DRAM based cache includes identifying, for each of a plurality of sets of the cache, the existence of a most recently used way that has not been accessed during a current assessment period; and for each set, refreshing only the identified most recently used way of the set not accessed during the current assessment period, while ignoring the remaining ways of the set; wherein a complete examination of each set for most recently used ways therein during the current assessment period constitutes a sweep of the cache.

2013004, Feb 14, 2013

Aug 11, 2011

13/207817

Robert D. Herzl - South Burlington VT, US
Kenneth A. Lauricella - Colchester VT, US
Arnold S. Tran - South Burlington VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 12/08

711122, 711136, 711E12017, 711E1202

A cache for use in a central processing unit (CPU) of a computer includes a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array; a least recently used (LRU) array configured to hold data indicating least recently used data entries in the data array; a line fill buffer configured to receive data from an address in main memory that is located external to the cache in the event of a cache miss; and a shadow register associated with the line fill buffer, wherein the shadow register is configured to hold LRU data indicating a current state of the LRU array.

6157981, Dec 5, 2000

May 27, 1998

9/085956

Bartholomew Blaner - Underhill Center VT
Henry Harvey Burkhart - Underhill VT
Robert Dov Herzl - South Burlington VT
Kenneth Anthony Lauricella - Colchester VT
Clarence Rosser Ogilvie - Huntington VT
Arnold Steven Tran - South Burlington VT

International Business Machines Corporation - Armonk NY

G06F 1200

711 3

A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.

2006004, Mar 2, 2006

Sep 1, 2004

10/711204

Robert Devins - Essex Junction VT, US
Paul Ferro - South Burlington VT, US
David Milton - Underhill VT, US
Arnold Tran - South Burlington VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

G06F 9/24

713002000

A method and apparatus for initializing multiple processors in an integrated circuit. Each processor is uniquely identifiable. Boot code for the initialization of the processors is written so that any specialized code for a specific processor is accessed using identity of the processor.