ARNOLD PAIGE
Broker in Natick, MA

4807258, Feb 21, 1989

Nov 17, 1987

7/121654

Richard W. Sieber - Attleboro MA
David A. Perreault - Reading MA
Arnold Paige - Natick MA

GTE Laboratories Incorporated - Waltham MA

H04L 700

375108

In a digital communication system including a central PABX subsystem coupled by a transmission line to a remote telephone subsystem, a method for establishing synchronization between the PABX and the telephone. The data format includes a message transmitted from the PABX to the telephone during the first half of a frame and a response transmitted from the telephone to the PABX during the second half of the frame. The synchronization method includes the steps of recognizing that synchronization has been lost, discontinuing transmission of responses by placing the line driver in a high impedance state while continuing transmission of messages, and detecting a valid message on the transmission line. The valid message is detected by finding in sequence, a message stop bit, the stop bit remaining on the line for one half frame and a message start bit. When a valid message is detected, transmission of responses is resumed.

5170160, Dec 8, 1992

Aug 12, 1991

7/759731

Michael Cooperman - Framingham MA
Richard W. Sieber - Attleboro MA
Arnold Paige - Natick MA

GTE Laboratories Incorporated - Waltham MA

H04Q 100

340825870

A broadband space tree-switch matrix establishes a desired switching path by sensitizing only the sequence of logic gates defined by the desired path such that only these sensitized logic gates are operable to undergo switching and thereby permit transmission of only the corresponding input signal. The tree-switch includes a plurality of cascaded stages wherein the first stage consists of dual-input NAND gates each receiving a corresponding input signal at one input and a control signal at another input. The remaining stages include a plurality of switching nodes each having a first NAND gate cascaded to a second NAND gate wherein the second NAND gate has a HIGH steady-state logic signal present at one of its inputs. An appropriate combination of control signals are applied to the NAND gates in the first stage to effect a selected switching path. A second broadband space switch matrix comprises a plurality of NAND gates arranged into a series of cascaded stages to form a tree-switch configuration.

5285202, Feb 8, 1994

Dec 11, 1991

7/808032

Michael Cooperman - Framingham MA
Richard W. Sieber - Attleboro MA
Arnold Paige - Natick MA

GTE Laboratories Incorporated - Waltham MA

H04Q 100

3408258

A broadband space switch matrix constructed from a plurality of NAND gates arranged into a set of cascaded stages to form a tree-switch multiplexing configuration. A plurality of input digital signals are applied to input ports coupled to the NAND gates in the first stage. A selected one of the input signals emerges as an output signal from an output port coupled to a single NAND gate in the last stage. Each NAND gate has a select line for receiving control signals. The switching path for the selected input signal is established by placing the sequence of NAND gates defined by the selected switching path in a state of conduction whereby only the selected input signal propagates through the switch. This is effected by forcing to a HIGH state the particular NAND gates in each stage whose outputs are coupled to the same NAND gate in the following stage along with the output of the NAND gate in the current stage which is in the chosen path. The forced HIGH state is achieved by applying a LOW state signal to the respective select lines of the particular NAND gates.

4970507, Nov 13, 1990

Mar 17, 1989

7/324848

Michael Cooperman - Framingham MA
Richard W. Sieber - Attleboro MA
Arnold Paige - Natick MA

GTE Laboratories Incorporated - Waltham MA

H04Q 100, H04N 710

342825800

A broadband switching array for equalizing the delay experienced by input signals as they propagate through their respective swtiching hpaths, and for providing output signals having uniform logical polarities. A cascaded set of delay means is connected to each of the input ports of the array in accordance with the amount of additional delay that is needed to accomplish equalization. Likewise, a cascaded set of inverter means is connected to each ouput port so that each switching path performs a common number of inversion operations, thereby allowing the output signals to have the same logical polarity.

5049877, Sep 17, 1991

Dec 13, 1990

7/626340

Michael Cooperman - Framingham MA
Richard W. Sieber - Attleboro MA
Arnold Paige - Natick MA

GTE Laboratories Incorporated - Waltham MA

H04Q 100

3408258

A broadband switching matrix having M. times. N crosspoint switches is arranged into a selected number of groups of vertically cascaded stages in which adjacent groups are interconnected with expansion stages. An input signal switched from row to column in a particular group propagates through the remaining stages in that group and then propagates successively through the expansion stages in each following group before reaching an output port. In another array configuration, a set of N multiplexers arranged in parallel each receive N input signals and provide a single output signal at a respective output port. The multiplexers are constructed from 2:1 selector elements which are arranged in a vertical tree configuration having log. sub. 2 N cascaded stages. Each multiplexer has the same number of stages and hence selector elements.

5465087, Nov 7, 1995

Feb 8, 1994

8/193819

Michael Cooperman - Framingham MA
Arnold Paige - Natick MA
Richard W. Sieber - Attleboro MA

GTE Laboratories Incorporated - Waltham MA

H04Q 100

3408258

A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.