ANTHONY ALOYSIUS IMMORLICA, JR
Pilots at Purgatory Rd, Mount Vernon, NH
License number
New Hampshire A2845428
Issued Date
Jun 2015
Expiration Date
Jun 2016
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
6 Purgatory Rd, Mount Vernon, NH 03057
Professional information
Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates
US Patent:
8304332, Nov 6, 2012
Filed:
Jun 1, 2011
Appl. No.:
13/150359
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 21/28
US Classification:
438582, 438571, 257E2124
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates
US Patent:
2010016, Jul 1, 2010
Filed:
Aug 31, 2007
Appl. No.:
12/086854
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-Chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Pane-Chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
International Classification:
H01L 29/812, H01L 21/283
US Classification:
257284, 438602, 257E21159, 257E29321
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates
US Patent:
2012020, Aug 16, 2012
Filed:
Jun 1, 2011
Appl. No.:
13/150352
Inventors:
Anthony A. Immorlica - Mont Vernon NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Pane-chane Chao - Nashua NH, US
Kanin Chu - Nashua NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 29/812
US Classification:
257280, 257E29317
Abstract:
A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
Method And Design Of An Rf Thru-Via Interconnect
US Patent:
2013034, Dec 26, 2013
Filed:
Jul 18, 2012
Appl. No.:
13/879696
Inventors:
Pane-chane Chao - Nashua NH, US
Bernard J. Schmanski - Merrimack NH, US
Anthony A. Immorlica - Mont Vernon NH, US
Kanin Chu - Nashua NH, US
Dong Xu - Nashua NH, US
Sue May Jessup - Windham NH, US
Bernard J. Schmanski - Merrimack NH, US
Anthony A. Immorlica - Mont Vernon NH, US
Kanin Chu - Nashua NH, US
Dong Xu - Nashua NH, US
Sue May Jessup - Windham NH, US
Assignee:
BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
International Classification:
H01L 23/373
US Classification:
257 77, 257 76, 438584
Abstract:
In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.