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Professional information
Low Noise Amplifiers With Transformer-Based Signal Splitting For Carrier Aggregation
US Patent:
2013031, Nov 28, 2013
Filed:
Aug 30, 2012
Appl. No.:
13/599919
Inventors:
Anosh Bomi Davierwalla - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03G 3/20
US Classification:
455208
Abstract:
Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier circuit, a transformer, and a plurality of downconverters. The amplifier circuit receives and amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The input RF signal includes transmissions sent on multiple carriers at different frequencies to a wireless device. The transformer includes a primary coil coupled to the amplifier circuit and a plurality of secondary coils providing a plurality of output RF signals. The plurality of downconverters downconvert the plurality of output RF signals with a plurality of local oscillator (LO) signals at different frequencies. Each downconverter includes a pair of mixers that receives one output RF signal and one LO signal and provides inphase and quadrature downconverted signals for one set of carriers being received.
Low Noise Amplifiers With Cascode Divert Switch For Carrier Aggregation
US Patent:
2013031, Nov 28, 2013
Filed:
Sep 10, 2012
Appl. No.:
13/608777
Inventors:
Anosh Bomi Davierwalla - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Aleksandar Miodrag Tasic - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H03G 3/20
US Classification:
455208, 4552341
Abstract:
Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes first and second amplifier circuits and a divert cascode transistor. Each amplifier circuit may include a gain transistor and a cascode transistor. The divert cascode transistor is coupled between the output of the first amplifier circuit and the gain transistor in the second amplifier circuit. The first and second amplifier circuits receive an input radio frequency (RF) signal including transmissions sent on multiple carriers at different frequencies to a wireless device. The first and second amplifier circuits and the divert cascode transistor are controlled to amplify the input RF signal and provide (i) one amplified RF signal for one set of carriers in a first operating mode or (ii) two amplified RF signals for two sets of carriers in a second operating mode.
Digitally-Controllable Delay For Sense Amplifier
US Patent:
7936590, May 3, 2011
Filed:
Dec 8, 2008
Appl. No.:
12/329941
Inventors:
Dongkyu Park - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mohamed Hassan Soliman Abu-Rahma - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Cheng Zhong - San Diego CA, US
Mohamed Hassan Soliman Abu-Rahma - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 11/00
US Classification:
365158, 365171, 365173
Abstract:
Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.
Multiple-Input Multiple-Output (Mimo) Low Noise Amplifiers For Carrier Aggregation
US Patent:
2013031, Nov 28, 2013
Filed:
Aug 24, 2012
Appl. No.:
13/593764
Inventors:
Aleksandar Miodrag Tasic - San Diego CA, US
Anosh Bomi Davierwalla - San Diego CA, US
Berke Cetinoneri - Encinitas CA, US
Jusung Kim - San Diego CA, US
Chiewcharn Narathong - Laguna Niguel CA, US
Klaas van Zalinge - La Jolla CA, US
Gurkanwal Singh Sahota - San Diego CA, US
James Ian Jaffee - Solana Beach CA, US
Anosh Bomi Davierwalla - San Diego CA, US
Berke Cetinoneri - Encinitas CA, US
Jusung Kim - San Diego CA, US
Chiewcharn Narathong - Laguna Niguel CA, US
Klaas van Zalinge - La Jolla CA, US
Gurkanwal Singh Sahota - San Diego CA, US
James Ian Jaffee - Solana Beach CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H03G 3/20
US Classification:
4552341
Abstract:
Multiple-input multiple-output (MIMO) low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a MIMO LNA having a plurality of gain circuits, a drive circuit, and a plurality of load circuits. The gain circuits receive at least one input radio frequency (RF) signal and provide at least one amplified RF signal. Each gain circuit receives and amplifies one input RF signal and provides one amplified RF signal when the gain circuit is enabled. The at least one input RF signal include transmissions sent on multiple carriers at different frequencies to the wireless device. The drive circuit receives the at least one amplified RF signal and provides at least one drive RF signal. The load circuits receive the at least one drive RF signal and provide at least one output RF signal.
Systems And Methods For Producing A Predetermined Output In A Sequential Circuit During Power On
US Patent:
8446188, May 21, 2013
Filed:
Apr 19, 2010
Appl. No.:
12/762992
Inventors:
Kashyap R. Bellur - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Christian Holenstein - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Christian Holenstein - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03L 7/00
US Classification:
327143
Abstract:
An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.
Differential Amplifier With Accurate Input Offset Voltage
US Patent:
2009018, Jul 30, 2009
Filed:
Jan 29, 2008
Appl. No.:
12/021477
Inventors:
Anosh B. Davierwalla - San Diego CA, US
Chul Kyu Lee - San Diego CA, US
Vannam Dang - San Diego CA, US
Chul Kyu Lee - San Diego CA, US
Vannam Dang - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03F 3/45
US Classification:
330253
Abstract:
An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.
System And Method Of Pulse Generation
US Patent:
8102720, Jan 24, 2012
Filed:
Feb 2, 2009
Appl. No.:
12/364127
Inventors:
Hari Rao - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Dongkyu Park - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Dongkyu Park - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 16/04
US Classification:
36518904, 365194, 36518905, 36518909
Abstract:
In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.
System And Method To Read And Write Data A Magnetic Tunnel Junction Element
US Patent:
8130534, Mar 6, 2012
Filed:
Jan 8, 2009
Appl. No.:
12/350304
Inventors:
Mohamed Hassan Abu-Rahma - San Diego CA, US
Seung-Chul Song - Austin TX, US
Sei Seung Yoon - San Diego CA, US
Dongkyu Park - San Diego CA, US
Cheng Zhong - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Seung-Chul Song - Austin TX, US
Sei Seung Yoon - San Diego CA, US
Dongkyu Park - San Diego CA, US
Cheng Zhong - San Diego CA, US
Anosh B. Davierwalla - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 11/00
US Classification:
365158, 365148
Abstract:
A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.
Memory Device For Resistance-Based Memory Applications
US Patent:
8228714, Jul 24, 2012
Filed:
Sep 9, 2008
Appl. No.:
12/206933
Inventors:
Anosh B. Davierwalla - San Diego CA, US
Cheng Zhong - San Diego CA, US
Dongkyu Park - San Diego CA, US
Mohamed Hassan Abu-Rahma - San Diego CA, US
Mehdi Hamidi Sani - Rancho Santa Fe CA, US
Sei Seung Yoon - San Diego CA, US
Cheng Zhong - San Diego CA, US
Dongkyu Park - San Diego CA, US
Mohamed Hassan Abu-Rahma - San Diego CA, US
Mehdi Hamidi Sani - Rancho Santa Fe CA, US
Sei Seung Yoon - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 11/00
US Classification:
365158, 365148, 36518911
Abstract:
In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.
Multiple Transmitter System And Method
US Patent:
2009022, Sep 10, 2009
Filed:
Mar 5, 2008
Appl. No.:
12/042362
Inventors:
Chulkyu Lee - San Diego CA, US
Anosh Davierwalla - San Diego CA, US
George Wiley - San Diego CA, US
Anosh Davierwalla - San Diego CA, US
George Wiley - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04B 3/00
US Classification:
375257
Abstract:
Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.