ANDY KATSU NGUYEN
Pharmacy at International Cir, San Jose, CA

6653873, Nov 25, 2003

Jul 19, 2002

10/198942

Andy T. Nguyen - San Jose CA

Xilinx, Inc. - San Jose CA

H03B 100

327112, 327108, 327391, 326 83

A driver circuit drives heavily loaded signals at high speeds with a reduced crowbar current. One-shots are used to drive the output pullup and pulldown, thereby minimizing the period when both devices are turned on. One embodiment includes an inverter, a one-shot low, a one-shot high, a pullup, and a pulldown. An input signal drives the inverter and the two one-shots. The inverter output terminal is coupled to the driver output terminal, as are the pullup and pulldown. The one-shot low circuit controls the pullup. The one-shot high circuit controls the pulldown. Another embodiment includes two pre-driver circuits, one controlling an output pullup and the other controlling an output pulldown. Each of the pre-driver circuits is implemented using a one-shot low and a one-shot high, as described above. One such embodiment is an output driver for a PLD, and the one-shots include various programmable options.

8026746, Sep 27, 2011

May 20, 2010

12/784075

Andy Nguyen - San Jose CA, US

Altera Corporation - San Jose CA

H03L 7/00

327143, 327142, 327198

Methods for controlling a Power On Reset (POR) circuit in an Integrated Circuit (IC) are presented. In one embodiment, a method includes an operation for gating a test POR signal configured to selectively disable an output of a POR circuit, and an operation for programming a fuse. The programming of the fuse includes operations for disabling the signal path of the test POR signal, and for enabling the output of the POR circuit. In another embodiment, the signal path of the test POR signal includes a pass gate, where permanently disabling the signal path is performed by disconnecting the pass gate.

6496044, Dec 17, 2002

Dec 13, 2001

10/016950

Hy V. Nguyen - San Jose CA
Gubo Huang - Milpitas CA
Andy T. Nguyen - San Jose CA

Xilinx, Inc. - San Jose CA

H03K 300

327108, 327112, 326 81

Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

7265586, Sep 4, 2007

Feb 25, 2005

11/067422

Gubo Huang - Milpitas CA, US
Andy T. Nguyen - San Jose CA, US
Ronald L. Cline - Albuquerque NM, US

Xilinx, Inc. - San Jose CA

H03K 19/0175

326 83, 326 38

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

6980035, Dec 27, 2005

Mar 18, 2003

10/391927

Gubo Huang - Milpitas CA, US
Shankar Lakkapragada - San Jose CA, US
Andy T. Nguyen - San Jose CA, US
Fariba Farahanchi - Los Gatos CA, US

Xilinx, Inc. - San Jose CA

H03B001/00, H03K003/00

327112, 327333

A technique and circuit implementation are described for automatically detecting a change in a power supply voltage and selectively reconfiguring a circuit for optimized performance at the changed voltage. One application of particular interest is an auto-detect level shifter. The auto-detect level shifter can be used in an output driver and can be automatically enabled if it is needed to optimize performance for various I/O standards, including those that operate at different voltages.

6847241, Jan 25, 2005

Jul 25, 2003

10/627457

Andy T. Nguyen - San Jose CA, US

Xilinx, Inc. - San Jose CA

H03L 706

327158, 327161, 327163, 377 69

Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.

7279982, Oct 9, 2007

Mar 24, 2005

11/089848

Andy T. Nguyen - San Jose CA, US
Gubo Huang - Milpitas CA, US

Xilinx, Inc. - San Jose CA

H03F 3/04

330301, 330 51

Low current differential signal/swing I/O interfaces and techniques can be implemented. An output interface converts input data signals to differential current signals for transmission over transmission lines. When the differential current signals are received by an input interface, they are converted to differential voltage signals and appropriately amplified.

8497712, Jul 30, 2013

May 18, 2012

13/475937

Andy Nguyen - San Jose CA, US
Ling Yu - Cupertino CA, US

Altera Corporation - San Jose CA

H03K 5/22

327 73, 327 72, 327 77, 327 87

A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.